TSMC ramps 2nm capacity 70%

- Taiwan Semiconductor Manufacturing Co. said April 28 that five 2-nanometer fabs will ramp this year, with 2nm capacity growing 70% annually through 2028. - Senior vice president and co-chief operating officer Kevin Zhang said first-year 2nm wafer output will be 45% above TSMC’s 2023 3nm launch. - The buildout extends a wider AI-driven squeeze across 3nm, packaging and overseas fabs. (cna.com.tw)

Taiwan Semiconductor Manufacturing Co. said its 2-nanometer production will expand fast enough to post a 70% compound annual growth rate from 2026 through 2028. (cna.com.tw) The company said five 2nm fabs will be ramping this year, with two in Hsinchu and three in Kaohsiung. Senior vice president and co-chief operating officer Kevin Zhang gave the update at TSMC’s recent North America Technology Symposium. (cna.com.tw) (tsmc.com) TSMC said its N2 process entered volume production in the fourth quarter of 2025 as scheduled. On TSMC’s technology page, the company says N2 uses first-generation nanosheet transistors, a design meant to improve speed and cut power use. (tsmc.com) In plain terms, a smaller process node lets chip designers pack more switching elements into the same area, like fitting more lanes onto the same highway. TSMC says N2 is its most advanced process for density and energy efficiency, aimed at energy-hungry computing workloads. (tsmc.com) The company’s own benchmark for the ramp is unusually aggressive: Zhang said first-year 2nm wafer output will be 45% higher than first-year 3nm output in 2023. TSMC also said 3nm capacity is still climbing, with a roughly 25% compound annual growth rate from 2022 through 2027. (cna.com.tw) That expansion is happening alongside a broader push to relieve bottlenecks tied to artificial intelligence chips. On April 16, Chairman and Chief Executive C.C. Wei said TSMC would add 3nm lines in southern Taiwan, Arizona and Kumamoto, and convert some Taiwan 5nm equipment to make 3nm chips. (cna.com.tw 1) (cna.com.tw 2) TSMC is also enlarging the packaging steps that turn finished wafers into usable AI processors. The company said CoWoS advanced packaging capacity is growing at more than 80% annually from 2022 through 2027, while SoIC 3D stacking capacity is growing at more than 90%. (cna.com.tw) Outside Taiwan, TSMC said output from its first Arizona fab in 2026 will be 80% higher than in 2025, and output from its first Kumamoto fab will be 130% higher. Those numbers show the company is trying to add supply in several places at once, not only at its newest node. (cna.com.tw) TSMC’s roadmap already stretches beyond N2. At its 2026 symposium, the company introduced A13, and its technology materials say N2P, an enhanced 2nm-family process, is scheduled for volume production in the second half of 2026. (tsmc.com 1) (tsmc.com 2) The immediate signal is that TSMC still sees AI demand outrunning normal build cycles at the most advanced nodes. The company is responding by adding fabs, repurposing tools and widening packaging capacity at the same time. (cna.com.tw 1) (cna.com.tw 2)

Get your own daily briefing

Scout delivers personalized news, insights, and conversations tailored to your role and industry.

Download on the App Store

Shared from Scout - Be the smartest in the room.