Die basics thread

An EUV optics engineer posted an illustrated X thread explaining what a die is, how wafers are diced, and why die size plus defect rates determine yield. (x.com) The thread (X status 2044451516124221890) includes step‑by‑step images and practical notes on dicing, reticle floorplanning, and yield impact. A die is a single integrated‑circuit chip cut from a processed silicon wafer after fabrication. (en.wikipedia.org) Singulation, or wafer dicing, is performed by scribing and breaking, mechanical sawing with diamond blades, laser cutting, or plasma dicing to separate individual dies. (oricus-semicon.com) Yield is commonly estimated with the Poisson model: yield ≈ e^(−D×A), where D is defect density and A is die area in mm². (calculator.academy) Using D = 0.5 defects/cm² (0.005 defects/mm²), a 100 mm² die gives yield ≈ e^(−0.005×100) ≈ 60.7%, while a 500 mm² die yields ≈ e^(−0.005×500) ≈ 8.2%. (calculatorultra.com) Dicing also consumes wafer area (kerf) and can chip edge dice, and papers on defect‑aware reticle floorplanning show non‑gridded layouts frequently cost dies during singulation. (thomasnet.com) Reticle defects and pattern placement errors replicate across many dies on every wafer; vendors like KLA emphasize reticle qualification to prevent mass yield loss. (kla.com) The thread closes by urging process and module planners to model die area, defect density, kerf losses and reticle layout before tape‑out to avoid surprised yield shortfalls. (x.com)