TSMC eyes Arizona packaging

- TSMC plans to open an advanced chip-packaging plant in Arizona by 2029 to keep more assembly local. - The company says packaging, not just fabrication, remains a bottleneck because wafers still often return to Taiwan for assembly. - TSMC is also delaying expensive High‑NA EUV tool deployment through 2029, signalling cost discipline despite strong AI demand. ( )

TSMC plans to add advanced chip packaging in Arizona by 2029, extending its U.S. buildout beyond wafer fabrication. (tsmc.com) Packaging is the stage that turns finished silicon into a usable processor by wiring dies, memory and substrates into one module. TSMC said Arizona-made wafers still often go back to Taiwan for that step, creating a supply-chain gap even after local fabrication starts. (msn.com) TSMC’s Arizona site in Phoenix has grown from a $12 billion project announced in 2020 to a planned $165 billion campus with six wafer fabs, two advanced packaging facilities and an research-and-development center. The first fab started high-volume production on its 4-nanometer process in the fourth quarter of 2024, the second targets 3-nanometer production in the second half of 2027, and the third is slated for 2-nanometer and A16 production by the end of the decade. (tsmc.com; tsmc.com) The company framed the U.S. expansion around artificial-intelligence demand from customers including Apple, Nvidia, Advanced Micro Devices, Broadcom and Qualcomm. In its March 4, 2025 announcement, TSMC said the Arizona packaging investment would help complete a domestic AI supply chain in the United States. (tsmc.com) Advanced packaging has become central because leading AI chips now rely on several pieces of silicon and stacks of high-bandwidth memory working as one product. TSMC’s Chip-on-Wafer-on-Substrate, or CoWoS, packaging line is being expanded to fit larger AI assemblies, including a 14-reticle version planned for production in 2028. (electronicsweekly.com) At the same April 2026 technology event, TSMC said it does not plan to use ASML’s newest High-NA extreme ultraviolet lithography tools in production through 2029. Deputy co-chief operating officer Kevin Zhang said the company can keep improving chips with current EUV systems instead. (electronicsweekly.com; theedgesingapore.com) Those High-NA machines cost more than €350 million each, according to Bloomberg’s reporting, and TSMC said they are “very, very expensive.” Bloomberg also reported TSMC’s 2026 capital spending could approach $56 billion as the company expands overseas and tries to protect margins. (theedgesingapore.com) TSMC is still pushing its roadmap forward without that tool change. The company said its A13 process is due for production in 2029, while A12 and new packaging and 3D-stacking options are also scheduled later in the decade. (electronicsweekly.com) The Arizona move leaves TSMC trying to localize more of the chipmaking chain while slowing one of the industry’s most expensive equipment upgrades. By 2029, the test for Phoenix is no longer just whether wafers can be made there, but whether they can stay there long enough to become finished AI chips. (tsmc.com; msn.com)

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