Intel’s EMIB‑T packaging report
A report says Intel’s EMIB‑T advanced packaging is slated for fab rollout this year as TSMC’s CoWoS capacity remains limited, positioning Intel’s packaging as a potential alternative for advanced AI accelerator designs. The briefing flags the source as less authoritative and frames the claim as directional: rivals may not need to out‑compete TSMC fully, only become credible at the margin. (startupnews.fyi)
The bottleneck in artificial intelligence chips is no longer just the chip. It is the package that has to hold giant compute dies next to stacks of high bandwidth memory, and Taiwan Semiconductor Manufacturing Company’s chip-on-wafer-on-substrate line has been so tight that the company said in April 2025 it was still working to double capacity in 2025 to meet demand. (tsmc.com) A package is the chip world’s version of a highway interchange. If the compute chip is the engine and high bandwidth memory is the fuel tank, the package is the dense web of roads that has to move data between them at very high speed without wasting too much power. (intel.com) Intel’s embedded multi-die interconnect bridge is one way to build that interchange. Instead of putting every chip on one giant slab of silicon, Intel buries a small silicon bridge inside the package substrate so separate chips can talk side by side. (intel.com) Intel’s embedded multi-die interconnect bridge-T adds through-silicon vias to that bridge. Those are tiny vertical holes through silicon, like elevator shafts in a building, and Intel says they help with shoreline-to-shoreline connections and make it easier to adapt designs that were built for other packaging approaches. (intel.com) That detail matters because the dominant rival system, Taiwan Semiconductor Manufacturing Company’s chip-on-wafer-on-substrate, uses a big silicon interposer under the chips. Intel is pitching embedded multi-die interconnect bridge-T as a way to get logic chips and high bandwidth memory connected with less silicon area and a simpler assembly flow. (intel.com) Intel has been moving this pitch from lab slides to foundry marketing. In March 2026, Intel said embedded multi-die interconnect bridge-T could support packaged systems larger than 6 times a reticle today, scale past 8 times a reticle in 2026, and reach more than 12 times by 2028 for artificial intelligence and high-performance computing parts. (community.intel.com) The new report says fab rollout could happen this year, but the sourcing is thin and the claim is best read as a directional signal, not a confirmed production milestone. That caution fits the rest of the market, where Intel has been publicly expanding its packaging story while outside reports still describe customer interest as early and opportunistic. (startupnews.fyi) (trendforce.com) The opening for Intel is not that Taiwan Semiconductor Manufacturing Company suddenly loses the market. The opening is that even after years of expansion, industry reports still describe chip-on-wafer-on-substrate capacity as constrained enough to push customers toward second-source packaging options. (trendforce.com 1) (trendforce.com 2) That is why this report is interesting even if the exact timing turns out to slip. In advanced packaging, a credible alternative does not need to beat Taiwan Semiconductor Manufacturing Company everywhere; it only needs to be good enough that a cloud company or accelerator designer can move one expensive program without waiting in the same line. (intel.com) (tsmc.com)
