TSMC shifts packaging for AI ASICs

Advanced packaging has become the choke point in AI chips. Not design. Not even leading-edge wafers, at least not by themselves. The hard part now is getting giant compute dies, HBM stacks, and I/O pieces stitched together at scale without waiting in the same line as Nvidia, AMD, and everyone else. That is why the latest supply-chain reporting matters — MediaTek is reportedly spreading its bets across TSMC and Intel packaging, and Google’s TPU v8e is said to be one of the first big proof points. (trendforce.com) ### What changed here? The new piece is not just “more AI demand.” The change is that MediaTek is reportedly using both TSMC’s CoWoS and SoIC and Intel’s EMIB, instead of treating advanced packaging as a one-vendor decision. For Google’s TPU roadmap, the reported split is especially telling: TPU v8t stays with TSMC’s N3P process and CoWoS-S, while TPU v8e is expected to use Intel EMIB. That is a real architectural sourcing decision, not a backup plan sitting in a drawer. (trendforce.com) ### Why is packaging suddenly the bottleneck? Because AI accelerators are no longer just one big chip. They are systems in a package. You need the compute die, memory stacks, substrate, interconnect, power delivery, and thermal behavior to all line up. TSMC’s CoWoS became the default answer for a lot of high-end AI silicon, but that success turned it into a queue. Once CoWoS capacity tightens, the constraint moves downstream — you can have designs ready and wafers reserved, but still miss deployment windows because the package cannot be built fast enough. (trendforce.com) ### Why would Google use EMIB? Basically, because Google does not need every TPU to make the exact same tradeoff. TrendForce says EMIB avoids the large interposer used in CoWoS by linking dies with embedded silicon bridges. That can help yield, reduce warpage risk, and scale package size differently. The catch is bandwidth density — EMIB is generally a worse fit than CoWoS for the most bandwidth-hungry, lowest-latency GPU-style designs. But for some ASIC layouts, that trade can be worth it if it gets you capacity, cost relief, or better scheduling. (trendforce.com) ### Why split v8t and v8e? Because the two chips do different jobs. Counterpoint says Google presented TPU v8t as the training part and TPU v8i as the inference part at Cloud Next, while separate industry reporting points to v8e as the next chip expected to use EMIB. The broader pattern is what matters — Google is no longer treating TPU manufacturing as one monolithic turnkey flow. It is disaggregating pieces of the stack, with MediaTek taking a larger role and packaging choices becoming workload-specific. (trendforce.com) ### Where does MediaTek fit in? MediaTek is trying to move from handset silicon into custom AI infrastructure. That is a much bigger jump than it sounds. The company has reportedly recruited Douglas Yu, a former TSMC advanced packaging leader tied to CoWoS and InFO, and analysts now see MediaTek as a serious AI ASIC contender. Counterpoint projects MediaTek could reach 26% of AI ASIC server compute shipments by 2028, approaching 5 million units, largely on the back of Google programs. ### Is this bad news for TSMC? Not really. It is more like a sign of overload than weakness. (counterpointresearch.com) TSMC still anchors the most important parts of these programs — process technology, CoWoS, and SoIC remain central. But when demand outruns one packaging lane, customers start designing around the bottleneck. That creates room for Intel to win packaging business without first winning the full foundry stack. ### What is the real takeaway? AI chip competition is shifting from “who has the best die” to “who can actually deliver the full package.” Packaging used to be the back-end detail. (english.cw.com.tw) Now it is shaping product definitions, supplier relationships, and rollout timing. If this reporting holds, Google and MediaTek are showing what the next phase looks like — not one perfect manufacturing path, but several good-enough ones that keep clusters shipping. (trendforce.com)