Siemens Deploys AI for Chip Design

The Siemens Questa One Agentic Toolkit represents a significant step in leveraging AI for chip design verification. This toolkit is designed to integrate with Siemens' broader Fuse EDA AI system, which combines generative and agentic AI to enhance productivity across the entire electronic design automation (EDA) workflow. The system utilizes a centralized multimodal data lake, allowing different AI tools to access information across what were previously siloed databases. At its core, the new toolkit features five distinct AI agents. These include an "RTL Code Agent" for generating synthesizable code, a "Lint Agent" to check for design errors, a "CDC Agent" for clock domain crossing verification, a "Verification Planning Agent" to create automated test plans, and a "Debug Agent" for analyzing failures. This approach aims to automate and accelerate many of the manual and time-consuming tasks involved in chip design. The register-transfer level (RTL) is a critical phase in chip design that models a digital circuit's data flow between hardware registers before the physical layout is created. The "sign-off" for this stage involves intensive verification to ensure the design is structurally sound and ready for the next steps of synthesis and implementation. Speeding up this verification process can significantly reduce the overall time-to-market for new chips. Siemens' initiative is part of a broader industry trend where AI is being integrated into EDA tools to manage the escalating complexity of modern chip design. Companies like Synopsys and Cadence are also developing AI-driven solutions to optimize for power, performance, and area (PPA), and to automate verification. The use of agentic AI, which can act autonomously to achieve goals, is seen as the next major step beyond AI copilots that merely assist engineers. The toolkit leverages NVIDIA's Nemotron models and NIM microservices, highlighting a key partnership in bringing advanced AI capabilities to the semiconductor industry. Early adopters of the technology, such as MediaTek, have reported immediate and significant productivity gains, with engineers becoming proficient within hours. This move toward AI-driven design automation is a response to the immense challenge of designing chips with billions of transistors. By automating routine tasks and optimizing complex design spaces, AI allows engineers to focus on more innovative and high-level architectural work. This shift is expected to not only accelerate design cycles but also lead to more efficient and powerful semiconductor devices.