ESP32-C5 Bug Fixed

The ESP32-C5 is one of Espressif's first RISC-V SoCs to feature dual-band Wi-Fi 6, targeting high-performance IoT applications that need stable, low-latency connectivity in congested wireless environments. Its 240 MHz processor and support for external memory are critical for devices like smart home hubs and industrial controllers. The bug addressed the interaction between two key features: PSRAM (Pseudo-Static RAM) and power-saving sleep modes. PSRAM allows developers to add megabytes of extra memory for data-intensive tasks, a feature often required in complex IoT devices. However, this external memory needs to be managed correctly, especially when the main chip enters low-power states. Sleep modes are fundamental for battery-powered IoT devices, allowing them to operate for months or years. In deep-sleep, most of the chip is powered down to conserve energy, but this creates a challenge in preserving the state of external components like PSRAM. Historically, interactions between external RAM and sleep states have been a source of subtle bugs in microcontrollers, sometimes leading to data corruption upon waking. A failure in the coexistence of PSRAM and sleep modes can lead to unpredictable behavior, such as crashes or data loss, which is particularly problematic for devices deployed in the field. For developers, such issues can be difficult to debug and can significantly delay product launches. The advisory provides a necessary software workaround to ensure system stability. This type of fix is part of the ongoing development and support for a hardware platform. Espressif Systems has a history of releasing such advisories and updates through its ESP-IDF (IoT Development Framework). This transparent process is crucial for the large open-source community that builds projects with ESP32 chips.