CoWoS emerges as packaging bottleneck

Advanced packaging is now one of the most important pieces of the AI chip business. Not the glamorous part. Not the leading-edge logic wafer everyone talks about. The backend. The layer where compute dies, HBM stacks, and the silicon interposer all get stitched into one giant package. The news this week is that Vanguard International Semiconductor said on May 5 it secured TSMC support for a new silicon interposer foundry line at its 12-inch Singapore fab — a sign that the bottleneck has moved downstream. (digitimes.com) ### What is CoWoS, really? CoWoS is TSMC’s chip-on-wafer-on-substrate packaging flow. Basically, instead of treating packaging like a plastic shell around one chip, CoWoS turns the package into part of the system. A big logic die — or several chiplets — sits beside stacks of high-bandwidth memory on a silicon interposer, which acts (digitimes.com)unts of data without blowing up power and latency. (trendforce.com) ### Why is the interposer the hard part? The interposer sounds secondary, but turns out it is load-bearing. It is a large piece of silicon with extremely fine routing, and it has to line up with multiple dies and HBM stacks at once. As packages get bigger, the inter(trendforce.com)o much larger later. Bigger package ambition means more pressure on interposer supply, yield, and assembly precision. (trendforce.com) ### So what changed this week? VIS joining the chain is the concrete development. DigiTimes says VIS won TSMC support for a new interposer line in Singapore and is pushing deeper into the CoWoS ecosystem. That matters because VIS is not just adding generic foundry(trendforce.com)raphic spread and, maybe more importantly, another place to expand constrained backend supply. (digitimes.com) ### Why is packaging the bottleneck now? Because front-end wafer capacity is no longer the only scarce thing. The AI package is now so complex that you can have finished compute dies and still be unable to ship the product at scale. Multiple industry reports still describe TSMC’s CoWoS lines as heavily booked through 2026, even as t(digitimes.com)rposer, or the HBM stack is late. (nextwavesinsight.com) ### Why does HBM keep showing up in this story? Because CoWoS and HBM are joined at the hip. The whole point of these AI packages is that the compute die sits right next to memory with extremely wide, short connections. If HBM is short, the package slips. If interposers are short, the package slips. If CoWoS lines are full, the pac(nextwavesinsight.com)es how many planes can actually leave. (nextwavesinsight.com) ### Who feels this first? Anyone shipping large AI accelerators. Nvidia gets the most attention, but the issue is broader than one company. AMD, Broadcom, Marvell, and custom silicon programs at hyperscalers all compete for the same class of advanced packaging resources. So the real fight is no longer just “who has the best chip design?” It is also “who reserved the package, the interposer, and the memory early enough?” (nextwavesinsight.com) ### Does this mean the bottleneck is fixed? No — it means the industry is finally treating the right bottleneck like a factory problem instead of a footnote. VIS adding interposer capacity is meaningful, but it is one move inside a much bigger scramble to scale CoWoS, HBM, substrates, and test. The bottom line is simple: in AI chips, packaging is no longer the last step. It is the gating step. (digitimes.com)