Vera Rubin CPO tests face bottlenecks
Testing for Nvidia’s Vera Rubin chips, which use co‑packaged optics (CPO), is reportedly hitting supply‑chain bottlenecks and prompting test‑equipment firms to race for solutions on advanced packaging flows. (x.com) Firms like Advantest and Teradyne are mentioned as working to address testing gaps tied to TSMC’s SoIC packaging approach. (x.com)
Nvidia’s next Vera Rubin systems are pushing chip testing into a new bottleneck: getting optical and advanced-package parts checked fast enough for volume manufacturing. (nvidia.com) Vera Rubin NVL72 combines 72 Rubin graphics processors, 36 Vera central processors, ConnectX-9 network cards and BlueField-4 data processing units in one rack-scale system, with Nvidia listing Quantum-X800 InfiniBand and Spectrum-X Ethernet for scale-out networking. Nvidia says the platform is part of its 2026 product cycle. (nvidia.com) Co-packaged optics means moving optical links next to the chip package, so data travels by light instead of longer copper traces. Nvidia said on March 18, 2025 that its photonics switches use that approach to deliver 3.5 times better power efficiency and 10 times better resiliency at scale than traditional designs. (nvidia.com) That shift changes the factory problem from only testing electrical signals to testing optical alignment, laser paths and package-to-package integration. Teradyne said co-packaged optics testing starts at the wafer stage and requires sub-micrometer fiber alignment, while most electrical probers are measured in tens of micrometers. (teradyne.com) Taiwan Semiconductor Manufacturing Co. is also adding complexity on the packaging side. TSMC says co-packaged optics will be critical above 50 terabits per second, that its 65-nanometer silicon photonics process is already in volume production, and that it is developing 3D stacked co-packaged optics technology for high-performance computing. (tsmc.com) That is why test-equipment vendors have been building new tooling before Vera Rubin reaches broad deployment. FormFactor and Advantest said on November 7, 2024 that they were developing a wafer-level test cell for silicon photonics and co-packaged optics aimed at high-volume manufacturing, built around Advantest’s V93000 system and automated nine-axis photonic alignment. (formfactor.com) Teradyne made the same pitch in June 2025, saying silicon photonics and co-packaged optics need scalable production test because optical chips must be checked again after singulation and before final integration. The company said the challenge is no longer just measuring faster chips, but measuring light-coupling accuracy repeatedly on a production line. (teradyne.com) Nvidia has already assembled a broad photonics supply chain around this transition. Its March 2025 announcement named TSMC, Coherent, Corning, Foxconn, Lumentum, Senko, SPIL, Sumitomo Electric Industries and other partners for silicon, optics and packaging. (nvidia.com) The immediate question is not whether co-packaged optics is coming; Nvidia, TSMC, Advantest and Teradyne have all positioned for it since 2024 and 2025. The question is whether test capacity, alignment tools and advanced-package flows can scale in time for Vera Rubin’s 2026 ramp. (nvidia.com)
