Intel’s Packaging Pivot

Intel’s first foundry opening may come from how it assembles chips, not from winning the race to the smallest transistor. Intel has spent the past year pushing customers toward advanced packaging such as EMIB and Foveros alongside its process roadmap. (intel.com) Packaging is the layer that connects separate pieces of silicon inside one product, like wiring together rooms in a building. Intel says its EMIB bridge has been in mass production since 2017 with both Intel and external silicon, and its Foveros line now spans 2.5D and 3D options for stacking or linking chiplets. (intel.com) At Intel Foundry Direct Connect on April 29, 2025, the company put packaging on the same stage as its leading-edge nodes. Intel introduced EMIB-T for future high-bandwidth memory needs and added Foveros-R and Foveros-B, while executives from MediaTek, Microsoft and Qualcomm joined the event. (intc.com) Intel is still advancing its manufacturing nodes, and it has said Panther Lake is its first client system-on-chip on Intel 18A. On October 9, 2025, Intel said Panther Lake was already in production and would enter high-volume production at Fab 52 in Arizona later that year. (newsroom.intel.com) The split emphasis reflects how chip design has changed in artificial intelligence and data center hardware. Instead of building one giant die, companies increasingly stitch together compute tiles and memory stacks inside one package, which makes the package itself part of the product’s performance. (intel.com) Intel has also tied that pitch to an industry standard. The company says it helped establish Universal Chiplet Interconnect Express, or UCIe, a die-to-die link meant to let chiplets from different vendors communicate inside one package, and the consortium says the UCIe 3.0 specification is now available. (intel.com) (uciexpress.org) That gives Intel a narrower sales path than asking a customer to move an entire chip design onto an unproven node. A chip company can keep a design on one manufacturing process, then buy Intel for the assembly, bridge, stacking, test, or subsystem work around that silicon. (intel.com) (eetimes.com) Industry analysts have argued that this is the more immediate commercial opening. EE Times reported in March 2025 that Intel Foundry was courting customers to shift designs from Taiwan Semiconductor Manufacturing Co.’s CoWoS packaging to Intel’s Foveros as demand for advanced-packaging capacity stayed tight. (eetimes.com) Intel’s own messaging now mirrors that sequencing. At its 2025 foundry event, the company described progress on “multiple generations” of process technology and advanced packaging, rather than presenting node leadership alone as the near-term proof point. (intc.com) (newsroom.intel.com) The practical test is whether Intel can turn that packaging pitch into repeat external business before its newest nodes win broad outside adoption. If that happens, Intel’s early foundry gains may show up first in the package around the chip, not the transistor inside it. (intel.com) (newsroom.intel.com)