EDA, IP post 86% gross margins

1/ The margin spread across semis is so wide because these businesses sell very different things. EDA and IP vendors sell reusable software and designs; foundries and OSATs sell capacity, yield and physical execution. That difference shows up directly in gross margin. (sec.gov) 2/ The “~86%” figure for EDA/IP lines up with how the category works. Arm says each CPU or compute platform can be licensed to multiple companies, creating economies of scale. Once the code base and architecture exist, another customer adds far less incremental cost than another wafer does at a fab. (sec.gov) 3/ Public-company numbers point the same way. Cadence reported fiscal 2025 non-GAAP operating margin of 44.6% on $5.297 billion of revenue and guided to 44.75%-45.75% for 2026, underscoring how profitable software-led design tools can be even before you get to the gross-margin layer. (investor.cadence.com) 4/ IP is similar, but even more obviously asset-light. Arm’s 2025 annual report says its business is built on licensing technology designs and collecting royalties on chips that ship later. That means one design effort can throw off revenue across many customers and many years. (sec.gov) 5/ Fabless chip companies usually sit below that. They often post strong gross margins because they own the architecture, software stack and customer relationship, but they still have to buy wafers, packaging and test from manufacturing partners. Nvidia’s annual report shows how much of that value can still be captured at the design layer. (sec.gov) 6/ Foundries look lower not because the business is weak, but because the cost base is heavier. TSMC reported 59.9% full-year 2025 gross margin and 50.8% operating margin, but those numbers sit on top of enormous fab, tool and process-investment requirements. (investor.tsmc.com) 7/ TSMC’s 2025 annual report also shows why “55% gross margin” can still be a capital-hungry business. The company said capital expenditures totaled US$29.76 billion in 2025, equal to about 24.3% of revenue, while the business also carries the fixed-cost burden of running leading-edge manufacturing at scale. (investor.tsmc.com) 8/ OSAT sits lower still because packaging and testing are more exposed to pricing pressure and utilization swings. ASE Technology Holding reported 17.7% consolidated gross margin for 2025, and its packaging-and-testing business gross margin was 23.8%, which is much closer to the “15%-20%” range cited in the value-chain breakdown than to EDA or IP levels. (media-aseholdco.todayir.com) 9/ Put simply: software and licensable IP scale almost infinitely; manufacturing scales by adding plants, tools, labor, materials and energy. That is why the top of the semiconductor stack can look like enterprise software economics, while the bottom looks like advanced industrial production. (sec.gov) 10/ That spread also explains why countries entering semis often start with assembly, packaging or test, while investors often prize design tools and IP. The first builds industrial capability; the second tends to capture more of the profit pool. The economics in current filings from Arm, Cadence, TSMC and ASE show exactly why. (sec.gov)