Intel’s EMIB‑T packaging rollout

A modern artificial intelligence chip is usually not one giant slab of silicon anymore. It is a cluster of smaller chips that have to sit side by side and talk at very high speed inside one package. (intel.com) That package is the part people used to treat like a fancy shipping box. In 2026, it is closer to a motherboard shrunk down to the size of your hand, with power delivery, heat removal, and ultra-short data links all packed together. (theregister.com) Intel’s news is that its next packaging step, called Embedded Multi-die Interconnect Bridge-T, is scheduled to enter production fabs this year. The “T” version adds vertical holes through the tiny silicon bridge so power and signals can move not just across the package but down through the bridge itself. (finance.yahoo.com) Intel’s older Embedded Multi-die Interconnect Bridge already used small silicon bridges buried in the package substrate instead of one huge silicon base under the whole chip. Intel says that lets it keep the expensive fine-pitch wiring only where the chiplets actually need to connect. (intel.com) The new version is aimed at two specific bottlenecks: high-bandwidth memory and chiplet links. Intel says demand for high-bandwidth memory raised the need for vertical power delivery with lower electrical noise, which is why it added through-silicon vias to Embedded Multi-die Interconnect Bridge-T. (intel.com) Intel is also designing for much bigger packages than the industry used to need. Reports on the 2026 rollout say Embedded Multi-die Interconnect Bridge-T can support packages up to 120 by 180 millimeters, with more than 38 bridges and over 12 reticle-sized dies in one package. (finance.yahoo.com) That scale fits the new artificial intelligence hardware map. Tom’s Hardware reported in February that Intel showed a test vehicle with four logic tiles and 12 stacks of high-bandwidth memory using Embedded Multi-die Interconnect Bridge-T. (tomshardware.com) The business twist is that Intel may not need to win the whole chip manufacturing job to make money here. Chief financial officer David Zinsner said on March 5 that Intel was close to packaging deals worth billions of dollars per year in revenue. (theregister.com) Reports published on April 7 said Intel has been in talks with Google and Amazon about packaging custom artificial intelligence processors. Neither relationship was confirmed publicly, but the reports tied those talks directly to Intel’s advanced packaging push. (finance.yahoo.com) That is why this rollout reaches beyond one chip technology. Intel is expanding packaging capacity in Rio Rancho, New Mexico, where Fab 9 opened in January 2024 as part of a $3.5 billion packaging investment, and it is adding assembly and test capacity in Penang, Malaysia. (newsroom.intel.com) (finance.yahoo.com) If packaging contracts really turn into a multibillion-dollar line of business, the winners will not just be chip designers. The work also pulls in substrate suppliers, testing lines, thermal engineers, design software firms like Keysight and Synopsys, and the real industrial footprint that sits near those teams. (keysight.com) (synopsys.com)