US onshoring hits $85B in fabs

Semiconductor onshoring in the U.S. just got a clean, concrete number — about $85 billion in fab projects are actively being built right now. That matters because “b(industrialinfo.com)lls across multiple states. The big cluster sits in Arizona, Ohio, and Idaho, with TSMC, Intel, and Micron carrying much of the weight. (industrialinfo.co([cnbc.com)s--357053)) ### Where does the $85 billion figure come from? The number comes from Industrial Info, which said on April 29 that it is tracking more (pr.tsmc.com) someday” money. It is the subset that has actually moved into active buildout. (industrialinfo.com) ### Which projects are doing the heavy lifting? TSMC’s Arizona site is the biggest symbol of the shift. The company’s U.S. plans have expanded dramatically, with federal CHIPS support finalized at up to $6.6 billion and the Arizon(industrialinfo.com) is the memory-side counterpart — a large domestic DRAM push instead of logic foundry capacity. (nist.gov) ### Is all of this arriving on time? Not really — and that is part of the story. Intel pushed Ohio back again, with the first fab now expected t(industrialinfo.com) “the build cycle is real, but messy.” TSMC and Micron look more advanced in near-term execution, especially with Micron’s Boise fab still targeting production around mid-2027. (cnbc.com) ### Why is Idaho suddenly in this conversation? Because Micron is not building a niche add-on. It is building a major memory manufacturing base in Boise, and the company has frame(nist.gov)hing it usually lacks in chip-policy talk — not just leading-edge logic, but domestic DRAM capacity too. (kivitv.com) ### Why does this matter beyond the fabs themselves? Because wafers are only part of the bottleneck now. Advanced packaging — especially CoWoS and related 3D integration steps — has become one of the tightest constraints in AI hard(cnbc.com)t Nvidia has reserved most of TSMC’s top-end packaging capacity. In plain English: even if you can make the chip, you still have to package it. (pr.tsmc.com) ### So does more fab construction solve the AI supply problem? Only partly. A fab gives you wafer capacity. AI syste(kivitv.com)ned labor. That is why onshoring arguments are getting broader. The goal is no longer just “have a fab in America.” It is “have enough adjacent capability that the fab is not stranded.” (cnbc.com) ### What is the catch for suppliers? Qualification. A supplier approved at one site is not automatically approved everywhere else, and moving parts, materials, or process steps across fabs can trigger fresh validation wor(pr.tsmc.com)city does not. This is an inference from how multi-site semiconductor manufacturing typically works, and it fits the current spread of projects. (industrialinfo.com) ### Bottom line? The $85 billion figure is a useful reality check. U.S. chip onshoring is no longer just a grants story or a geopolitical talk(cnbc.com)nding just as AI shifts the bottleneck from the fab floor to the packaging line. (industrialinfo.com)