Packaging is the battleground now
Foundry economics are shifting away from node shrinks toward packaging — 2.5D/3D stacking and chiplets are becoming the competitive battleground. That shift turns many hardware buys into system‑definition decisions, so opportunities should be classified by offering type and integration burden rather than treated as a single, flat pipeline. (digitaltoday.co.kr)
Advanced packaging — the wiring and stacking that turns separate silicon pieces into one processor — is now where chip performance and cost are being decided. TSMC, Intel, and Samsung are all pitching packaging as a core foundry service, not a finishing step. (tsmc.com) (intel.com) (samsung.com) Traditional chipmaking shrinks transistors on a single die, but advanced packaging splits a design into chiplets and reconnects them inside one package. The Universal Chiplet Interconnect Express consortium says its standard is meant to let companies “mix and match” chiplets from multiple vendors inside one system-on-chip. (uciexpress.org) Taiwan Semiconductor Manufacturing Company’s CoWoS, short for Chip on Wafer on Substrate, places logic chiplets and high-bandwidth memory on a large interposer, a silicon base that acts like a dense internal circuit board. TSMC says CoWoS-S can support an interposer up to about 2,700 square millimeters, and markets it for artificial intelligence and supercomputing chips. (tsmc.com) Intel is making the same case with Foveros, its stacking technology for placing active dies on a base die with through-silicon vias, or vertical connections drilled through silicon. Intel says Foveros 2.5D uses face-to-face bonding with a 36-micron microbump pitch and can be paired with Embedded Multi-die Interconnect Bridge, or EMIB, to build larger packages beyond a single reticle limit. (intel.com) Samsung Foundry is selling both side-by-side and vertical versions. Samsung says its I-Cube line handles 2.5D horizontal integration, while X-Cube stacks logic dies on the Z-axis, and it is pitching both around artificial intelligence, fifth-generation wireless, and automotive workloads. (samsung.com) The customer products already show why this changed. Advanced Micro Devices says its Instinct MI300 series combines up to 8 vertically stacked accelerator dies, 8 stacks of High-Bandwidth Memory 3, and 4 input-output dies in one package, turning packaging into part of the architecture itself. (amd.com) That changes how buyers evaluate foundry capacity. Taiwan Semiconductor Manufacturing Company said in its 2024 annual report that strong demand for “leading-edge logic and advanced packaging technologies” helped drive a 30% year-over-year revenue increase in U.S. dollar terms, and the company said it manufactured 11,878 products for 522 customers in 2024 using advanced, specialty, and advanced packaging services. (tsmc.com) (sec.gov) The bottleneck is no longer only who can print the smallest transistor. It is who can assemble logic, memory, thermal control, power delivery, and die-to-die links into a package that meets a customer’s schedule, because the package now defines much of the system the buyer is actually purchasing. (tsmc.com) (intel.com) (uciexpress.org)
