SpaceX Boosts In‑House Chips; Pad Pull
New industry coverage says SpaceX is scaling in-house ASIC and FPGA work for Starship and Starlink electronics — and a recent last-minute removal of a Super Heavy booster from the pad was analyzed as likely tied to sensor or verification anomalies, reported and analyzed. The combination highlights rising pressure on flight electronics, real-time diagnostics, and HIL test regimes in LA’s aerospace hub.
SpaceX is building a fan-out panel-level packaging (FOPLP) plant in Texas that sources say is targeting volume production in late Q3 2026 globalsmt.net. SpaceX opened a large PCB factory in Bastrop, Texas in 2025 and currently lists active FPGA/ASIC design roles under the title "FPGA/ASIC Design Engineer" on its careers board, confirming hiring for silicon and FPGA teams newswav.com. Starlink’s recent satellite generation incorporates AMD Versal adaptive SoCs, according to reporting on components used in the constellation pcmag.com. SpaceX has stated its Gen3 Starlink plan would allow a single Starship launch to add roughly 60 Tbps of capacity to the network, underscoring the throughput demands pushing custom compute and FPGA work. datacenterdynamics.com. Industry coverage and supply‑chain reporting link SpaceX’s packaging and in‑house chip moves to a desire to reduce dependence on STMicroelectronics and Taiwan suppliers, a trend echoed in broader semiconductor strategy analyses from PwC and trade outlets tomshardware.com. Two independent video analyses posted to YouTube examined a last‑minute Super Heavy booster removal from the pad and highlighted sensor/verification signals as the likely proximate cause, while a contemporaneous SpaceX statement and reporting flagged a pre‑launch gas‑system pressure anomaly on Booster 18 during Nov. 21, 2025 testing at Starbase. youtube.com. Public reporting has repeatedly tied recent Starship scrubs to ground‑systems and sensor issues, with outlets documenting postponements driven by unresolved telemetry and ground verification checks ahead of launch windows cbsnews.com. Hardware‑in‑the‑Loop (HIL) testing is cited across aerospace vendors as indispensable for rocket avionics validation, with technical vendors and integrators describing HIL as the method for fault insertion and real‑time sensor emulation before flight campaigns blog.pickeringtest.com. The Aerospace Corporation’s Embedded System Applications Center operates flight‑equivalent HIL rigs for avionics verification, and DLR’s HiLT lab documents using dSPACE real‑time platforms and TTEthernet hardware for deterministic testing—evidence of the exact test infrastructure SpaceX and contractors would need to scale for Starship/Starlink electronics verification. aerospace.org.
