UALink Standard Challenges Proprietary Interconnects

- The UALink Promoter Group consists of industry heavyweights AMD, Broadcom, Cisco, Google, HPE, Intel, Meta, and Microsoft, with the broader consortium now exceeding 85 members, including AWS and Apple. - The UALink 1.0 specification, finalized in April 2025, details a high-speed interconnect for up to 1,024 AI accelerators within a single computing pod. It uses a modified Ethernet physical layer to achieve a bidirectional data rate of 200 GT/s per lane, reaching up to 800 GT/s in a four-lane configuration. - In a direct comparison with its primary target, Nvidia's NVLink, UALink 1.0 supports a larger number of accelerators (1,024 vs. 576 for NVLink 5.0). However, NVLink 5.0 currently offers higher per-GPU bandwidth at 1.8 TB/s versus UALink 1.0's 800 Gb/s. - UALink is designed for "scale-up" workloads, connecting accelerators densely within a rack or pod, and is intended to be complemented by the Ultra Ethernet standard, which handles "scale-out" networking between pods. - While the 1.0 specification is complete, the first hardware products featuring UALink are not expected to reach customers until at least 2026. IP and validation tools are already being offered by companies like Synopsys to accelerate development. - Broadcom, a founding member, is also promoting its own "Scale-Up Ethernet" technology, arguing it can deliver similar capabilities sooner by adapting existing Ethernet hardware, creating a competing open standard narrative. - The roadmap for UALink includes future versions that will add features like memory coherency and virtualization, which are already present in Nvidia's NVLink. There are also plans for a 128G specification that will align with the PCIe Gen 7 standard for different use cases.