Francesco Manni, Salvatore Levantino speak

- Francesco Manni and Salvatore Levantino are scheduled to present SHIFT-backed talks at ESSERC 2026 in Palma de Mallorca on September 7-10, 2026. (esserc2026.org) - Levantino’s workshop abstract cites a 10-12 GHz PLL core with 14.9 femtoseconds integrated jitter in integer-N mode and 25.4 femtoseconds fractional-N. (esserc2026.org) - The talks appear in workshop W8 at ESSERC 2026, where organizers list millimeter-wave and 6G hardware topics including Ka-band integration. (esserc2026.org)

Francesco Manni and Salvatore Levantino are appearing in the same ESSERC 2026 workshop as European researchers push from device-level advances toward more integrated millimeter-wave hardware. The conference website lists both presentations in workshop W8, “Recent advances in millimeter-wave and 6G hardware design using BiCMOS and SiGe technologies,” held during the September 7-10 event in Palma de Mallorca, Spain. (esserc2026.org 1) (esserc2026.org 2) The workshop is framed within the SHIFT Chips Joint Undertaking project, which the program expands as “Sustainable tecHnologies enablIng Future Telecom applications.” The pairing matters because the two talks sit on opposite ends of the same radio chain. Manni’s topic is front-end-module integration at Ka-band using SiGe and GaN custom chipsets, while Levantino’s is ultra-low-jitter frequency generation in 55-nm BiCMOS for millimeter-wave systems, according to the workshop listing and the social posts that first highlighted the session. ### Why are these two talks being grouped together? Workshop W8 is organized around “recent advances in millimeter-wave and 6G hardware design using BiCMOS and SiGe technologies,” and the conference program says it emphasizes system-level optimization through co-design of circuits, antennas and signal processing. (esserc2026.org) The same abstract also lists “integration challenges through compact Ka-band front-end modules combining SiGe and GaN technologies” and “ultra-low-jitter frequency generation techniques” as core topics. That makes the Manni and Levantino talks complementary rather than overlapping. (esserc2026.org) One addresses how to combine different semiconductor technologies in the transmit-receive front end; the other addresses how to generate a spectrally clean local oscillator signal that such front ends need at higher frequencies. That connection is an inference from the workshop description and published research on the cited circuits. ### What is Francesco Manni working on at Ka-band? Francesco Manni is affiliated with the Electronic Engineering Department at the University of Rome Tor Vergata, according to IEEE author information and a published chapter on Ka-band GaN-on-SiC power amplifiers for satellite phased arrays. (esserc2026.org) His research profile says he is pursuing a Ph.D. in space systems and technologies with interests in RF power amplifier theory, design, linearization and efficiency-improving techniques. A recent publication bearing Manni’s name describes a Ka-band transmitter-only phased-array architecture for 25.5-27 GHz satellite applications built around a custom AlGaN/GaN power amplifier. (esserc2026.org) That work reported 20 dB of gain and 28 dBm saturated power for the amplifier stage and targeted 70 dBm effective isotropic radiated power for the array. The ESSERC workshop description does not publish Manni’s full abstract, but it places his talk in the conference’s discussion of compact Ka-band modules combining SiGe and GaN. (ieeexplore.ieee.org) ### What is Salvatore Levantino scheduled to present? Salvatore Levantino’s session is listed as “Breaking the Jitter Barrier: Ultra-Low-Jitter Frequency Generation in 55-nm BiCMOS for mm-Wave Systems.” The conference program says the work presents a frequency-generation suite in 55-nm BiCMOS and reports a 10-12 GHz PLL core with integrated jitter of 14.9 femtoseconds in integer-N mode and 25.4 femtoseconds in fractional-N mode. The same abstract says the design uses a power-gated LC oscillator acting as a digital-to-time converter and a series-resonance digitally controlled oscillator. (taylorfrancis.com) It also says a 56-76 GHz sextupler complements the PLL and includes a digitally calibrated tripler with more than 40 dB of fundamental rejection, targeting 6G backhaul and satellite communications. ### Why does 55-nm BiCMOS show up here alongside SiGe and GaN? Politecnico di Milano says Levantino’s research focuses on mixed-signal and RF circuits, including low-phase-noise oscillators and frequency synthesizers for wireless systems. (esserc2026.org) A 2026 Journal of Solid-State Circuits paper co-authored by Levantino describes a 28-38 GHz digitally assisted frequency tripler in 55-nm SiGe BiCMOS, supported by the SHIFT project under Chips Joint Undertaking grant 101096256. The workshop’s own framing ties those process choices together. (esserc2026.org) ESSERC says the session will cover BiCMOS and SiGe circuit techniques, compact Ka-band front-end integration with GaN, and low-noise amplifier and power-amplifier trade-offs for 6G and other high-frequency links. ### Where can readers track the next step? ESSERC 2026 is running in Palma de Mallorca from September 7 through September 10, and workshop W8 is listed on the conference program page. The website names Philippe Ferrari of University Grenoble Alpes and Christophe Gaquière of MC2 Technologies as workshop chairs, and lists Levantino’s talk in the 09:30-10:00 session slot. (levantino.faculty.polimi.it) (esserc2026.org) (esserc2026.org)

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