Nvidia: AI speeds chip design
Nvidia said AI reduced a GPU design task that previously took 10 months and eight engineers to an overnight job, while stressing fully automated chip design remains distant. (tomshardware.com) Company commentary framed this as an example of AI feeding back into semiconductor design velocity and iteration. (tomshardware.com)
Nvidia said its artificial intelligence tools now do one chip-design job overnight that once took eight engineers about 10 months. (tech.yahoo.com) The task is called porting a standard cell library: rebuilding a catalog of tiny logic blocks that chip designers reuse when they move to a new manufacturing process. Bill Dally, Nvidia’s chief scientist, said that library can contain roughly 2,500 to 3,000 cells. (videocardz.com) Dally described the work during a March 2026 conversation with Google chief scientist Jeff Dean at Nvidia’s GTC conference in San Jose. Nvidia’s on-demand session page identifies the talk as “Advancing to AI’s Next Frontier,” featuring Dally and Dean. (nvidia.com) A standard cell library is basic chip plumbing: prebuilt parts for functions like logic gates and flip-flops that engineers combine into larger circuits. When a chip company changes process technology, those parts have to be redone so they meet the new factory’s rules for size, power and timing. (research.nvidia.com) Nvidia said the speedup does not mean a graphics processing unit can now design an entire processor by itself. Dally said the company is still “a long way” from fully autonomous chip design, even as it applies artificial intelligence across design exploration, library work, bug handling and verification. (tomshardware.com) The company has been building these tools for years. In October 2023, Nvidia researchers published ChipNeMo, a family of domain-adapted large language models for chip-design work such as engineering chatbots, script generation, and bug summarization. (research.nvidia.com) Nvidia researchers also published work in June 2024 on using large language models for standard cell layout optimization, a narrower version of the same problem Dally highlighted this month. The paper said advanced nodes create more routing and design-rule constraints as manufacturers push toward 2-nanometer processes. (research.nvidia.com) The pitch inside Nvidia is that faster internal tools let engineers try more versions of a design before tape-out, the point when a chip layout is sent to a factory. Dally’s example turned 80 person-months of repetitive work into a single overnight run, but Nvidia is still describing the software as an assistant for engineers, not a replacement for them. (tech.yahoo.com)
