Intel inks Google tie‑up and bets on packaging

Intel just got Google to commit to more of the chips that keep data centers running, even as the market obsesses over giant artificial intelligence accelerators. On April 9, Intel and Google said they would work together across multiple future generations of Intel Xeon server processors and custom infrastructure chips for Google’s cloud systems. (intel.com) The first piece of that deal is the familiar one: central processing units, or the general-purpose brains that coordinate work across a server. Intel said Google Cloud already uses Xeon 6 in its C4 and N4 instances for artificial intelligence coordination, inference, and ordinary computing jobs. (intel.com) The second piece is the newer one: infrastructure processing units, which are chips that act like a building’s back-office staff, handling networking, storage, and security so the main processors can spend more time on customer workloads. Intel said the Google partnership expands co-development of custom application-specific integrated circuit versions of those infrastructure chips. (intel.com) Google and Intel have been building that infrastructure chip relationship for years, and this announcement extends it deeper into the artificial intelligence buildout. Reuters reported on April 9 that the expanded partnership is aimed at artificial-intelligence-focused central processing units and custom infrastructure processors as cloud companies shift from training models to deploying them at scale. (reuters.com) That shift matters because running artificial intelligence all day for users is not the same as training one giant model once. Inference workloads need servers that move data efficiently and predictably, which is why Intel is pitching a combination of Xeon processors plus infrastructure chips instead of talking only about graphics processing units. (reuters.com / intel.com) At the same time, investors are watching a different part of Intel’s business: packaging, which is the step where separate chip pieces and memory stacks get wired together into one finished module. In modern artificial intelligence hardware, that assembly step has become a bottleneck because the fastest chips often depend on advanced packaging as much as on the silicon itself. (intel.com) Intel’s answer is Embedded Multi-die Interconnect Bridge-T, or EMIB-T, which uses small silicon bridges inside the package instead of a giant full-size base layer under the whole chip. Intel says that design can build packages larger than six times a single reticle today, more than eight times this year, and more than twelve times by 2028. (intel.com) A reticle is the stencil used to print circuits onto silicon, and its size limits how large one chip can be in a single shot. Intel’s packaging pitch is that if one chip cannot get bigger cheaply, you split the design into smaller chiplets and reconnect them inside the package like city blocks linked by short bridges. (intel.com) That puts Intel directly against Taiwan Semiconductor Manufacturing Company’s Chip-on-Wafer-on-Substrate, or CoWoS, which is the packaging method behind many top artificial intelligence accelerators. Reports this month said demand for CoWoS remains tight and that Google and Amazon have been discussing Intel packaging as a second source for custom artificial intelligence chips. (trendforce.com / techspot.com) Intel’s own finance team has been signaling that packaging could turn into real foundry revenue before its contract manufacturing of full wafers does. Chief financial officer David Zinsner said in March that packaging was “the more interesting part” of Intel Foundry and that Intel was close to deals worth billions of dollars per year in packaging revenue. (theoutpost.ai) So this week’s Google announcement landed as more than a normal customer renewal. It told the market that Intel is still inside one of the world’s biggest clouds on the processor side, and it kept alive the bigger bet that Intel can also sell the assembly technology that future artificial intelligence chips may need when Taiwan’s packaging lines are full. (intel.com / trendforce.com / techspot.com)