TSMC Pauses High-NA Move

TSMC says it will not use ASML’s newest High-NA chipmaking machines through 2029, choosing lower equipment costs over an earlier jump to the latest toolset. (bloomberg.com) High-NA extreme ultraviolet lithography is the machine that prints the tiniest circuit patterns onto silicon, like a stencil for transistors. TSMC Deputy Co-Chief Operating Officer Kevin Zhang said those systems cost more than €350 million, or about $410 million, each. (bloomberg.com) Instead, TSMC told customers in Santa Clara on April 22 that it can keep shrinking chips with ASML’s current extreme ultraviolet tools. Reuters reported the newer High-NA systems are about $400 million each, roughly double the cost of older extreme ultraviolet machines. (finance.yahoo.com) TSMC paired that message with a longer roadmap. The company said A13 will enter production in 2029, A12 is also scheduled for 2029, and N2U is scheduled for 2028. (tsmc.com) A13 is a direct shrink of A14, and TSMC said it delivers 6% area savings over A14 with design rules that stay backward compatible. TSMC also said N2U offers 3% to 4% higher speed or 8% to 10% lower power than N2P, with a 1.02x to 1.03x logic-density gain. (tsmc.com) The roadmap also moved A16 later. Coverage of the symposium said A16 volume production is now slated for 2027, not 2026. (trendforce.com) That stance puts pressure on ASML’s rollout plans. ASML has told investors it is targeting High-NA high-volume manufacturing readiness by the end of 2026, with customer insertion in 2027 and 2028. (asml.com) TSMC is the world’s largest contract chipmaker and builds processors for companies including Nvidia, Apple and Google, so its tool choices shape supplier demand across the industry. Bloomberg said TSMC is ASML’s largest customer, while Reuters said TSMC is betting its research team can extract more performance from the installed base it already has. (bloomberg.com) (finance.yahoo.com) TSMC also used the symposium to shift attention toward packaging, the method for linking several chips and memory stacks into one larger computing package. Reuters reported TSMC said that by 2028 it expects to stitch together 10 large chips and 20 memory stacks, up from current artificial-intelligence packages such as Nvidia’s Vera Rubin with two compute chips and eight high-bandwidth-memory stacks. (finance.yahoo.com) The message from Santa Clara was that TSMC still plans smaller nodes, just not with the most expensive new scanner in this cycle. Through 2029, the company’s roadmap says the next gains will come from squeezing more out of current lithography and combining more chips inside the same package. (tsmc.com) (finance.yahoo.com)