TSMC plans 25K PIC wafers/month
- TrendForce said on July 8 that TSMC’s photonic integrated circuit capacity is projected to rise from about 500 wafers monthly to 25,000 by 2028. - The key milestone is 10,000 wafers a month in the second quarter of 2026, with Nvidia and Broadcom identified as early COUPE users. - TSMC’s next public checkpoint is its 2026 second-quarter results page, where investors track packaging and photonics-related capacity updates.
TrendForce’s July 8 report on TSMC’s photonic integrated circuit ramp is a supply-chain story before it is a foundry story. The headline number is large — about 25,000 PIC wafers a month by 2028 from roughly 500 today — but the more important detail is the shape of the ramp: 10,000 wafers a month by the second quarter of 2026 and 15,000 by the fourth quarter. That matters because silicon photonics has spent years as a promising architecture and a limited manufacturing business. A wafer roadmap of this size suggests TSMC’s COUPE platform is moving from pilot-scale relevance toward something the AI networking supply chain can actually plan around. TrendForce said Nvidia and Broadcom are among the early customers being watched for that first volume phase. (trendforce.com) A useful way to read this is not “TSMC will make a lot of optical chips,” but “the bottleneck is shifting.” Once PIC wafer output rises, pressure moves downstream into optical engines, packaging, test, validation, yield management, and system integration. ### Why does a PIC wafer number matter so much? TSMC’s forecast matters because photonic integrated circuits are one of the core building blocks behind co-packaged optics and other short-reach optical interconnect schemes aimed at AI clusters. (trendforce.com) As bandwidth demand rises, vendors are trying to move more data with lower power and shorter electrical paths than copper links allow. Nvidia has already described its co-packaged optics work with TSMC as part of a broader platform for data-center connectivity. In Nvidia’s account, the effort combines optical and electrical components to improve bandwidth density and power efficiency in next-generation AI infrastructure. ### What exactly is TSMC scaling here? (developer.nvidia.com) TrendForce’s report points specifically to TSMC’s PIC capacity and ties it to the company’s COUPE platform. Earlier TrendForce reporting said TSMC’s roadmap called for qualification in small-form-factor pluggables in 2025, followed by CoWoS-based co-packaged optics integration in 2026. (developer.nvidia.com) That distinction matters. A PIC wafer is not a finished optical module, switch, or accelerator package. It is one piece of a stack that still requires lasers, electrical ICs, advanced packaging, assembly, and production test before a cloud customer can deploy anything at rack scale. That is why wafer growth by itself does not settle the commercial picture. ### Why are Nvidia and Broadcom the names to watch first? TrendForce identified Nvidia and Broadcom as early COUPE customers, and other secondary reports on the same roadmap have also pointed to AMD joining the first wave of volume users. (trendforce.com) The common thread is that all three sit close to the highest-bandwidth AI and networking workloads, where optical interconnect economics are most urgent. Nvidia’s own public material already places TSMC inside its photonics collaboration stack. Broadcom, meanwhile, has been one of the most visible advocates of optical scaling in switch silicon and data-center interconnect. The customer mix in the first wave therefore looks less like broad adoption and more like targeted deployment by companies already pushing cluster bandwidth limits. (trendforce.com) ### Where does the opportunity move if wafers stop being scarce? The next constraint is likely to sit in integration and validation. A faster PIC ramp creates demand for firms that can handle optical packaging, co-design between electronic and photonic dies, reliability testing, and manufacturing bring-up around advanced packages. That is an inference from the structure of the supply chain, not a statement TrendForce made directly. It follows from the fact that PIC wafers are upstream inputs to more complex optical systems. (developer.nvidia.com) The timing also matters. TSMC’s investor relations page lists its 2026 second-quarter results materials, which gives the market a near-term checkpoint for any new commentary on advanced packaging and adjacent capacity plans. (investor.tsmc.com) (trendforce.com)