UK Project Unveils RISC-V Testbed for Satellite Workloads
The ExCALIBUR H&ES project in the UK has unveiled a new testbed based on the open-source RISC-V architecture. The platform is designed for evaluating scientific and data-science workloads relevant to satellite and aerospace applications. Hardware includes physical boards like the Milk-V Pioneer and Lichee Pi 4A, as well as soft-core RISC-V processors implemented on Xilinx FPGAs, providing a platform for exploring performance and reliability.
- The overarching ExCALIBUR programme is a £45.7 million UK initiative designed to prepare high-priority scientific and industrial applications for the transition to exascale supercomputing. It is led by the Met Office and UK Research and Innovation (UKRI) to redesign software and algorithms for future hardware architectures. - The selection of RISC-V is significant for aerospace due to its open-source, modular instruction set architecture (ISA), which allows for custom, license-free processor designs tailored for specific mission requirements like fault tolerance and real-time processing. This contrasts with proprietary ISAs and supports the development of sovereign technology capabilities. - The Milk-V Pioneer board provides a high-performance, server-class development platform within the testbed, featuring a 64-core SOPHON SG2042 processor running up to 2.0 GHz, support for up to 128 GB of DDR4 RAM, and a standard mATX form factor with PCIe 4.0 slots. - For edge AI and ML workloads, the Lichee Pi 4A board includes a T-HEAD TH1520 quad-core RISC-V SoC with an integrated 4 TOPS Neural Processing Unit (NPU), supporting frameworks like TensorFlow and ONNX for AI acceleration. - The use of Xilinx FPGAs allows researchers to prototype and test "soft-core" RISC-V processors, enabling deep customization of the CPU architecture itself for specific workloads, which is a key advantage for exploring novel approaches to hardware acceleration in resource-constrained satellite systems. - This testbed is funded under the ExCALIBUR Hardware and Enabling Software (H&ES) programme, a £4.5 million sub-project focused on providing researchers with early access to novel, pre-commercial hardware to co-design future systems. - The European Space Agency (ESA) is also increasingly adopting RISC-V for space missions to reduce reliance on proprietary processors and foster innovation, developing its own System-on-Chip designs and supporting IP cores for the architecture.
