TSMC’s CoWoS surge
TSMC is dramatically expanding CoWoS advanced‑packaging capacity, growing at roughly an 80% CAGR and targeting about 120–130k wafers/month by the end of 2026. (x.com) Reported capacity commitments show Nvidia reserved more than half of that space for Blackwell/Rubin GPUs while rivals like AMD face very large wafer needs (MI400 cited at roughly 150k wafers), and current yields are advertised in the 70–80% range to support these ramps. (x.com)
TSMC is racing to expand the packaging step that turns AI chips into usable processors, aiming for roughly 120,000 to 130,000 CoWoS wafers a month by the end of 2026. (trendforce.com) CoWoS, short for Chip-on-Wafer-on-Substrate, is TSMC’s method for placing a logic chip and stacks of high-bandwidth memory side by side on a silicon base so they can move data faster. TSMC says the platform is built for high-performance computing and supports large interposers and multiple memory stacks in one package. (tsmc.com) Supply-chain reports cited by TrendForce and DigiTimes say TSMC’s CoWoS capacity is now around 75,000 to 80,000 wafers a month and is being pushed toward the 120,000 to 130,000 range by late 2026. TrendForce said the expansion is spilling over to outsourced assembly and test partners as TSMC tries to relieve the shortage. (trendforce.com, digitimes.com) Nvidia has booked most of that future capacity, according to DigiTimes and follow-on reports that put its 2026 reservation at about 800,000 to 850,000 wafers for Blackwell Ultra and Rubin products. Wccftech, citing DigiTimes, said that amount is more than half of TSMC’s projected 2026 CoWoS output. (digitimes.com, wccftech.com) That matters because packaging, not wafer fabrication, has become the choke point for AI accelerators that use several chiplets and large memory stacks. TSMC said in its 2024 annual report that demand for leading-edge logic and advanced packaging helped drive record results, tying CoWoS directly to the company’s current AI boom. (investor.tsmc.com) Nvidia’s product roadmap is one reason the queue is so long. Nvidia announced its Rubin AI platform in January 2026 after the Blackwell generation, and both families rely on dense packaging to connect compute dies and memory at very high bandwidth. (nvidianews.nvidia.com, tsmc.com) Rivals are chasing the same lines. DigiTimes said AMD’s MI400 program alone could require roughly 150,000 wafers, a figure that shows how one major launch can consume more than a month of TSMC’s planned 2026 CoWoS capacity. (digitimes.com) The manufacturing problem is not just volume but yield, the share of packages that come out usable. A supply-chain report carried by SmBom said CoWoS-L, the version used for newer Nvidia designs, has been running around 70% to 80% yield, versus much higher levels for older CoWoS-S packaging. (smbom.com) TSMC is also widening the supply base around the bottleneck. TrendForce said outsourced semiconductor assembly and test companies are taking on more advanced packaging work, while TechNews figures cited by TrendForce put end-2026 CoWoS capacity in a broader 115,000 to 140,000 wafer-a-month range. (trendforce.com, trendforce.com) The result is that the hardest part of building an AI chip is no longer only etching the silicon. In 2026, the race also runs through the packaging plants that bond those chips to memory and decide how many Blackwell, Rubin, and MI400 systems can actually ship. (tsmc.com, digitimes.com)
