Intel leans on packaging, not nodes

Intel is talking less like a chip company that must win every transistor race and more like a company that can make other people’s chips work together in one giant package. On April 9, Intel and Google announced a multiyear AI infrastructure deal, and Intel’s foundry team has been pushing a packaging technology called Embedded Multi-die Interconnect Bridge-T that is built for very large AI parts. (intel.com, intel.com) For years, the bragging rights in semiconductors came from the wafer node, which is the factory process that shrinks circuits so more computing fits on one slice of silicon. Intel is still chasing new nodes, but its newer pitch is that advanced packaging can join many separate chip pieces the way a motherboard joins parts inside a PC, only much faster and much closer together. (intel.com, intel.com) That shift starts with a bottleneck at the center of the artificial intelligence boom. The most in-demand AI accelerators increasingly use huge packages with high bandwidth memory, and the industry has been constrained by limited capacity for Taiwan Semiconductor Manufacturing Company’s Chip-on-Wafer-on-Substrate packaging, better known as CoWoS. (startupnews.fyi, intel.com) Intel’s answer is Embedded Multi-die Interconnect Bridge, or EMIB, which puts a small silicon bridge inside the package substrate so neighboring chip pieces can talk without needing one giant slab underneath them. Intel says the newer Embedded Multi-die Interconnect Bridge-T version adds through-silicon vias, which are tiny vertical connections through the bridge, and that makes it easier to support logic chips linked to high bandwidth memory in large AI designs. (intel.com, intel.com) Intel’s foundry group said last month that Embedded Multi-die Interconnect Bridge-T can scale packaged systems to more than 8 times a reticle this year and more than 12 times by 2028. A reticle is the maximum chip area a lithography tool prints in one shot, so getting past that limit is how companies build AI parts that are too large to make as one monolithic die. (intel.com) That is why Intel’s sales pitch now sounds like “bring us the design you already wanted to build somewhere else.” Intel says Embedded Multi-die Interconnect Bridge-T can help convert designs from other packaging approaches, while reducing silicon use and avoiding some wafer-level assembly steps that a full silicon interposer package requires. (intel.com, intel.com) The Google deal shows the other half of the strategy. Intel said Google will keep using Intel Xeon central processing units across artificial intelligence inference, cloud, and general-purpose workloads, and the two companies will also co-develop custom application-specific integrated circuit infrastructure processing units. (intel.com) That sounds less glamorous than “build the fastest graphics processor,” but it matches how modern AI systems actually work. Google’s own cloud stack already mixes Tensor Processing Units, central processing units, networking, and software across clusters that can scale to 9,216 Ironwood chips, so the machine that serves AI is already a collection of specialized parts rather than one magic processor. (blog.google, cloud.google.com) Intel is betting that if the scarce thing in AI is no longer just the chip but the way chips, memory, and links are assembled, then packaging becomes a chokepoint you can sell. That is a different comeback plan from the old Intel script, because it treats the package, the supply chain, and the partnership as the product. (intel.com, intel.com)