TSMC adds US packaging

- TSMC plans to open an advanced chip‑packaging plant in Arizona by 2029 to expand onshore assembly capacity. - The facility will prioritise advanced packaging like CoWoS and 3D‑IC while delaying high‑NA EUV adoption through 2029. - This selective onshoring strengthens packaging resilience without immediately deploying the most expensive next‑generation lithography tools. ( )

Taiwan Semiconductor Manufacturing Co. plans to open an advanced chip-packaging plant in Arizona by 2029, adding a missing step in its U.S. chip supply chain. (reuters.com) Kevin Zhang, TSMC’s deputy co-chief operating officer, told Reuters the company is seeking permits for the project and aims to bring CoWoS and 3D integrated-circuit packaging to the Arizona site before 2029. CoWoS is the method used to connect multiple chips in one package for artificial-intelligence processors from customers such as Nvidia. (reuters.com (digitimes.com)) Packaging is the assembly stage after wafer-making, when separate chips and memory are stacked or linked together so they work as one product. That step has become a bottleneck for AI hardware, and TSMC said in January that it was applying for permits for its first advanced-packaging plant in an existing Arizona facility. (reuters.com (tsmc.com)) The Arizona move extends TSMC’s broader U.S. buildout, which the company said in March 2025 would reach $165 billion and include six fabs, two advanced-packaging facilities and a research center. TSMC’s Arizona site says its first fab is already in volume production, its second fab is targeting production in 2027, and its third fab is targeting production by the end of the decade. (tsmc.com 1) (tsmc.com 2)) TSMC is pairing that packaging push with a slower timetable for the newest lithography tools. DigiTimes reported that TSMC’s roadmap through 2029 does not include high-numerical-aperture extreme ultraviolet machines, the next generation of chip-printing equipment. (digitimes.com) High-NA EUV is the sharper version of the light-based tool used to print tiny circuit patterns onto wafers. ASML, the only supplier, says its first High-NA system can print features 1.7 times smaller than earlier EUV systems and is aimed at sub-2-nanometer logic production. (asml.com 1) (asml.com 2)) That leaves TSMC adding assembly capacity in Arizona without immediately installing the most expensive next-wave lithography there. Reuters reported the company is looking for a “very diverse manufacturing footprint,” while keeping the most advanced process rollout paced over several years. (reuters.com) (tsmc.com)) Arizona is also becoming a second U.S. packaging hub. Amkor said its $2 billion packaging and test facility in Peoria, Arizona, is expected to create 2,000 jobs by 2028, with groundbreaking held on October 6, 2025. (amkor.com 1) (amkor.com 2) If TSMC hits its 2029 target, chips made in Arizona would no longer need to leave the state for one of the most specialized finishing steps. That would give U.S. customers more local capacity for the part of chipmaking that AI demand has strained the most. (reuters.com)

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