TSMC adds U.S. packaging capacity
- TSMC plans to open a chip-packaging plant in Arizona by 2029 to expand advanced packaging capacity. - The company also showcased a new chip generation it says avoids the need for the costliest high-NA EUV tools. - Expanded packaging could ease compute constraints for robotics hardware over the long term, but the 2029 timeline leaves near-term scarcity intact ( ).
TSMC says it plans to open an advanced chip-packaging plant in Arizona by 2029, extending its U.S. buildout beyond wafer-making into a bottleneck that now limits many artificial-intelligence chips. (reuters.com) Packaging is the step that connects finished pieces of silicon into one working chip system, and it has become critical as Nvidia, Apple and other designers split processors across multiple chiplets. Reuters reported that TSMC executive Kevin Zhang said the Arizona site is targeted for 2029. (reuters.com) TSMC had already said on March 4, 2025 that its enlarged U.S. plan would include two advanced-packaging facilities, alongside three new fabs and an research-and-development center, taking its total planned U.S. investment to $165 billion. The company says its Arizona site now employs more than 3,000 people, and its first fab has been in volume production since late 2024. (tsmc.com, tsmc.com) The timing matters because advanced packaging, not just wafer production, has turned into a choke point for AI hardware. CNBC reported on April 8 that Nvidia had reserved most of TSMC’s top-end packaging capacity, underscoring why U.S. customers want assembly and test closer to Arizona wafer fabs. (cnbc.com) For now, the near-term squeeze does not go away. TSMC and Amkor said in October 2024 that TSMC would use Amkor’s planned Peoria, Arizona facility for turnkey advanced packaging and test services, including technologies such as Integrated Fan-Out and Chip on Wafer on Substrate, or CoWoS. (tsmc.com) TSMC paired the packaging update with a roadmap pitch on manufacturing tools. At its April 22, 2026 North America Technology Symposium in Santa Clara, the company introduced its A13 process and told Reuters it expects to keep shrinking chips without using ASML’s costlier high-numerical-aperture extreme ultraviolet machines. (tsmc.com, reuters.com) TSMC said A13 is a direct shrink of A14, offers 6% area savings over A14, keeps A14-compatible design rules, and is scheduled for production in 2029. Reuters reported that TSMC’s message to customers was that it could deliver smaller, faster chips while delaying adoption of ASML’s newest and most expensive lithography gear. (tsmc.com, reuters.com) That combination — more U.S. packaging and a node roadmap that leans on existing extreme ultraviolet tools longer — gives customers a clearer picture of where capacity may open up at the end of the decade. It does not change the calendar: TSMC’s own target for Arizona packaging is still 2029. (reuters.com, tsmc.com)
