TPU orders pressuring TSMC capacity
Reports say rising TPU orders are competing for advanced TSMC capacity, tightening foundry availability and complicating silicon supply dynamics. That pressure is a lever in short‑term procurement conversations about availability and lead times. (themarketsdaily.com)
MediaTek is reported to have won orders for Google's v7e and v8e TPUs and asked TSMC for roughly a 7× increase in CoWoS packaging capacity, with about 10,000 CoWoS wafers annually tied to Google in 2026. (trendforce.com) Multiple outlets say Google trimmed its 2026 TPU production target from roughly 4.0 million units to about 3.0 million units because access to TSMC’s CoWoS advanced‑packaging slots is constrained. (abit.ee) Industry analysis shows nearly every major AI accelerator (Nvidia’s Rubin, Google’s TPU v7/v8, Amazon Trainium3, AMD’s MI350X) moving to TSMC’s N3 node in 2026, with SemiAnalysis estimating AI could consume ~86% of N3 capacity and utilization effectively exceeding 100%. (the-decoder.com) Reports link CoWoS and HBM4 packaging shortages to delivery risk for new GPUs and accelerators, with recent pieces flagging potential delays to Nvidia’s Rubin lineup amid tight HBM4 availability. (benzinga.com) Analysts cited by MarketBeat and others point to hyperscaler TPU bookings as a major driver behind near‑term TSMC utilization and pricing power, a dynamic that underpins current procurement conversations about lead times and capacity allocations. (marketbeat.com) TSMC is reportedly planning fab retrofits and capacity expansions to materially increase output by 2028, even as its 2nm capacity is described as effectively fully booked by large customers—signalling constrained foundry availability through the mid‑to‑late 2020s. (rallies.ai)
