Open Source RISC-V CPU Project Releases Update
The open-source SERV project has announced the 1.3 release of what it calls "the world’s smallest RISC-V CPU." The ultra-compact design is intended for deeply embedded, resource-constrained environments like sensor nodes or low-power controllers. Recent updates have focused on feature enhancements within the same minimal hardware area, making it accessible for rapid prototyping.
- The CPU's minimal size is achieved through a bit-serial architecture, where data is processed one bit at a time, significantly reducing the required logic gates compared to parallel designs. - Created by Olof Kindgren, SERV originated from a 2018 contest to design the smallest or fastest RISC-V CPU capable of running the Zephyr Real-Time Operating System (RTOS). - While the base core implements the RV32I instruction set, optional extensions are available, including the 'M' extension for integer multiplication and division and the 'C' extension for compressed instructions, which can reduce program memory size. - The "CoreScore" benchmark is used to measure how many SERV cores can be instantiated on a single FPGA, with a record of 6,000 cores set on a Xilinx VCU128 device, utilizing 98.5% of its Look-Up Tables (LUTs). - The reference System-on-Chip (SoC) for the CPU is called "Servant," which provides the necessary peripherals to run the Zephyr RTOS and has been ported to more than 26 different FPGA boards. - Beyond FPGAs, the SERV core has an established path to silicon fabrication through the open-source OpenLANE toolchain, targeting the SkyWater 130nm process development kit (PDK). - Future development concepts include "DSRV" and "QERV," which would use 2-bit and 4-bit datapaths, respectively, to increase performance at the cost of a slightly larger hardware footprint. - A project in collaboration with Harvard and Pragmatic Semiconductor resulted in a physically flexible, non-silicon version of the SERV processor, as published in the journal *Nature*.
