Siemens and TSMC expand AI tie

Siemens said on April 22 that it is expanding its collaboration with Taiwan Semiconductor Manufacturing Co. to bring more artificial intelligence into semiconductor design. (siemens.com) The announcement covers AI-assisted automation across the electronic design automation workflow, including automated fixing of design-rule-check violations and integration with Siemens’ Fuse EDA AI system. (siemens.com) (eenewseurope.com) A design rule check is the software step that flags whether a chip layout breaks the foundry’s manufacturing rules, and it can become a bottleneck as process nodes shrink. Siemens said the new work aims to automate parts of that cleanup with its Calibre and Aprisa tools. (eenewseurope.com) (siemens.com) The companies also widened support for 3D integrated circuits, which stack multiple dies in one package and create new alignment, heat and connectivity problems. Siemens said its Calibre 3DStack and 3DThermal tools now support interface checks, inter-chiplet design-rule checks and thermal analysis for TSMC 3DFabric technologies. (siemens.com) (electronicsforyou.biz) Siemens said its EDA toolset has achieved certifications for TSMC’s N3A, N3C, N2P, A16 and A14 process technologies. Those certifications span physical verification, place-and-route, custom design and simulation tools used before a chip can be taped out for manufacturing. (siemens.com) (tsmc.com) TSMC has been building that ecosystem through its Open Innovation Platform, which links foundry process technologies to outside electronic design automation vendors. Its EDA Alliance lists partners that provide tools for layout, timing, simulation, verification and signoff. (tsmc.com) The 3D packaging part is not new from scratch. TSMC said in 2024 that it was already using artificial intelligence and machine learning with ecosystem partners to improve 3D integrated-circuit productivity and quality of results. (tsmc.com) Siemens and TSMC had already expanded their relationship in September 2025 around 3D integrated circuits and AI-driven circuit and systems design. The April 2026 announcement pushes that work further into automated rule fixing, agent-based workflow orchestration and newer process-node certifications. (siemens.com 1) (siemens.com 2) The immediate pitch is speed: fewer manual fixes in physical verification, more certified tools at advanced nodes, and more software support for stacked-chip designs that are becoming standard in artificial-intelligence hardware. (siemens.com) (tsmc.com)