Synopsys debuts hardware‑assisted verification

A chip team can spend months proving a design works before it ever sends the file to a factory, because one hidden bug in a processor cache or memory link can turn a $50 million tape-out into scrap. Synopsys is selling a way to run much more of that proof on specialized hardware instead of waiting on slower software-only simulation. (synopsys.com) That job is called verification, and it is the chip industry’s version of rehearsing every scene before opening night. Synopsys says modern artificial-intelligence chips now need quadrillions of verification cycles before silicon exists, because large language models are doubling in size about every four months and interface data rates are doubling every three years. (synopsys.com) The hardware doing this work is usually an emulator or a field-programmable gate array, which is a rewireable chip engineers use like a physical stand-in for the real design. Synopsys says running verification on those boxes lets teams start software bring-up earlier and validate performance and power before the final chip is manufactured. (synopsys.com) The new pitch is “software-defined” verification, which means Synopsys is trying to add speed and features through software updates without forcing customers to replace the hardware rack. The company says that approach can lift ZeBu Server 5 performance by up to 2x and scale capacity by up to 2x for very large multi-die designs. (synopsys.com) Synopsys also added two 12-field-programmable-gate-array systems called HAPS-200 12F and ZeBu-200 12F, replacing earlier 6-field-programmable-gate-array versions in the middle of its lineup. The company says those new platforms double emulation and prototyping capacity for mainstream mobile, client, server, consumer, and edge artificial-intelligence designs. (synopsys.com) The more unusual part is test automation built into the hardware-assisted flow itself. Synopsys says its new tools can automatically stress corner cases in processor, memory, and input-output subsystems, and can check full-system coherency under realistic workloads before the chip exists. (synopsys.com) Coherency is the rulebook that keeps many processor cores from reading stale data when they share memory, and it is one of the easiest places for rare bugs to hide. Synopsys says the new hardware-assisted tests are built to catch those cache-coherency and subsystem-level failures earlier, when fixing them is still a design change instead of a product recall. (synopsys.com) The announcement also reaches into mixed-signal chips, where digital logic has to interact with analog behavior from things like power circuits and data converters. Synopsys says real-number model emulation lets teams approximate that analog behavior inside faster digital verification flows, so software and hardware can be tested together sooner. (engineering.com) AMD showed up in the launch because these verification boxes are built around advanced field-programmable gate arrays and large server processors. Synopsys said joint optimization with the AMD Vivado software stack and AMD EPYC processors cuts compile times and gets customers to accurate system models faster. (synopsys.com) This is the part of the semiconductor race most people never see: not who has the best model demo, but who can close coverage and trust the silicon before production starts. If Synopsys can really turn existing verification hardware into a faster, more automated test lab through software updates, it gives chip teams one more way to move from design to tape-out without adding another long hardware replacement cycle. (synopsys.com)