AMD signs MOU with Samsung for HBM4

Memory is the story here — not just chips. AI servers are now constrained by how much data they can keep close to the processor, how fast they can move it, and whether vendors can actually get enough of the right memory on time. That is why the March 18 AMD-Samsung announcement matters. The two companies signed an MOU that ties Samsung’s HBM4 to AMD’s next Instinct MI455X accelerator and next-generation DDR5 to EPYC “Venice” CPUs inside AMD’s Helios rack plans. (amd.com) ### What did AMD and Samsung actually sign? They signed a memorandum of understanding — not a finished purchase contract for every module AMD will ever buy. But this is still a real supply-chain signal. AMD and Samsung said they will expand their collaboration around next-generation AI memory and computing, w(amd.com) for 6th Gen EPYC “Venice” CPUs. Lisa Su and Samsung vice chairman Young Hyun Jun appeared together at the signing in Pyeongtaek, Korea. (amd.com) ### Why is HBM4 the big deal? HBM4 is the stacked memory that sits right next to the AI GPU. Basically, it is the difference between a very fast accelerator and an accelerator stuck waiting for data. Samsung says its commercial HBM4 runs at 11.7 Gbps, can scale to 13 Gbps, and reaches up to 3.3 TB/s of bandwidth per stack. That is the kind of jump vendors need as model sizes and inference loads keep rising. (news.samsung.com) ### Which AMD product gets it? AMD named the Instinct MI455X directly. That matters because it pins the deal to a specific upcoming accelerator instead of vague “future products” language. AMD already framed the next generation of its AI racks around MI400-series-era systems and Helios reference designs, so the memory partnership is really about making that roadmap manufacturable, not just marketable. (amd.com) ### Where does DDR5 fit in? The easy mistake is to think this is only a GPU-memory story. It is also a host-memory story. AMD said the MOU covers next-generation DDR5 solutions for EPYC processors and the Helios platform. In plain English, AMD wants Samsung helping on both the accelerator-side memory pool and(amd.com)ad where the CPU still has to hold a lot of state. (amd.com) ### Why mention “Venice” and “Helios”? Because AMD is selling a rack, not a part. “Venice” is the codename for 6th Gen EPYC, and Helios is AMD’s next AI rack reference design that combines Instinct GPUs, EPYC CPUs, and Pensando networking. The point of naming all three is to show the memory deal spans the whole system. Samsung is not just filling a BOM line item — it is being woven into AMD’s rack-scale AI plan. (amd.com) ### Is this also about supply security? Yes — maybe more than anything else. HBM supply has been one of the hardest choke points in AI hardware. Nvidia’s rise made that painfully obvious, and memory vendors gained unusual leverage because accelerator roadmaps can slip if the right HBM is late or yield-constra(amd.com)y at scale. That does not guarantee perfect supply, but it lowers a real execution risk. (news.samsung.com) ### How does this fit AMD’s bigger AI push? AMD has been moving from standalone GPUs toward full rack-scale systems. Its recent roadmaps tie together Instinct GPUs, EPYC CPUs, ROCm software, and reference racks designed for dense AI deployment. The Samsung deal fits that shift exactly. If AMD wants to compete system-on-system instead of chip-on-chip, it needs memory partnerships that cover the whole stack. (amd.com) ### Bottom line? This is not just “AMD buys memory from Samsung.” It is AMD trying to lock down the hardest part of the next AI server build — high-bandwidth GPU memory plus enough coordinated CPU memory to make the whole rack useful. If Helios is AMD’s answer to the AI factory era, this MOU is part of how it makes that answer real. (amd.com)