Synopsys adds multi‑die AI tool support in deeper TSMC design partnership

Synopsys said on April 22 that it expanded its design and intellectual-property partnership with Taiwan Semiconductor Manufacturing Co., or TSMC, for advanced AI chips. (news.synopsys.com) The update covers TSMC’s 3-nanometer and 2-nanometer process families, plus A16 with Super Power Rail and A14, which are among the foundry’s newest manufacturing platforms. (news.synopsys.com) (engineering.com) At the center of the announcement is multi-die design, which splits one large processor into several smaller chiplets and links them inside one package. Synopsys said its 3DIC Compiler now supports TSMC 3DFabric technologies including SoIC and CoWoS at interposer sizes up to 5.5 times reticle scale. (news.synopsys.com) (engineering.com) That matters because advanced AI systems are no longer just one chip on a board. They are increasingly stacks of compute dies, memory, interconnects, and packaging that have to be checked together for heat, power delivery, and signal loss. (engineering.com) (news.synopsys.com) Synopsys said it linked 3DIC Compiler with RedHawk-SC, RedHawk-SC Electrothermal, and Ansys HFSS so engineers can analyze power integrity, temperature, and high-speed signal behavior in the same workflow. The company also said that collaboration on RedHawk-SC, Totem, and HFSS-IC Pro expands from TSMC A16 to A14. (engineering.com) (news.synopsys.com) The companies also tied the partnership to co-packaged optics, which places optical links next to processors to move more data with less electrical bottleneck. Synopsys said its multiphysics enablement for TSMC’s COUPE platform combines optical, photonic, electromagnetic, thermal, and electrical simulation tools. (news.synopsys.com) (engineering.com) On the design-automation side, Synopsys said it is working with TSMC on agentic run assistance in Fusion Compiler for A14 designs using TSMC NanoFlex Pro architecture. It also said AI-assisted physical verification in IC Validator is being developed to find and fix design-rule violations faster before tapeout. (news.synopsys.com) (engineering.com) Synopsys paired those software updates with new interface blocks that chip designers license instead of building from scratch. The company said it achieved successful silicon bring-up of low-power M-PHY v6.0 intellectual property on TSMC N2P and taped out 64-gigabit UCIe and 224-gigabit connectivity IP aimed at next-generation AI systems. (news.synopsys.com) TSMC framed the work as part of its Open Innovation Platform ecosystem and its 3DFabric packaging push for AI and high-performance computing customers. Synopsys framed it as a way to move engineers from chip-level design toward system-level signoff before manufacturing. (news.synopsys.com) The partnership does not announce a new chip customer or a financial deal. It shows where the bottlenecks are shifting: less in drawing transistors, more in making many dies, links, and cooling systems work as one package. (news.synopsys.com) (newelectronics.co.uk)