Intel Preps Nova Lake Desktop CPUs
Intel is preparing its next-generation Nova Lake-S desktop CPU family, which will feature significant architectural changes including a dual-compute tile design and a new “bLLC” (big Last Level Cache). The new processors are positioned to challenge competitors in high-performance markets like industrial automation and edge AI. On the mobile front, initial benchmarks of the Core Ultra 7 355 (Panther Lake) show it significantly trails the higher-end Ultra X7, highlighting the performance gap between its mainstream and flagship mobile chips.
- Nova Lake's architecture will introduce "Coyote Cove" Performance-cores and "Arctic Wolf" Efficiency-cores, representing two generations of architectural advancement beyond the "Lion Cove" and "Skymont" cores in Arrow Lake. This new architecture, combined with a die fabricated on TSMC's 2nm process, is expected to significantly increase both single-threaded and multi-threaded performance. - To compete with AMD's 3D V-Cache, select Nova Lake processors will feature "big Last Level Cache" (bLLC), which integrates a large L3 cache directly onto the compute die rather than stacking it separately. Leaks suggest configurations with up to 144MB of bLLC per compute tile, with dual-tile designs potentially offering a total of 288MB. - The Nova Lake desktop platform will utilize the new LGA 1954 socket to accommodate the increased power and I/O requirements of the new chips, which could feature up to 52 cores (16 P-cores, 32 E-cores, and 4 LP E-cores). The accompanying 900-series chipsets, such as the Z990, will support this with a significant increase in connectivity, offering up to 48 total PCIe lanes. - Panther Lake's mobile processors are built on Intel's 18A process node, which is the company's first to implement both RibbonFET gate-all-around transistors and PowerVia backside power delivery. This advanced manufacturing process aims to deliver a significant improvement in performance per watt. - The integrated GPU in Panther Lake, based on the Xe3 "Celestial" architecture, features a larger L2 cache (increased from 8MB to 16MB) and improved resource utilization compared to the previous Xe2 architecture. This results in reduced memory interface traffic and is designed to boost graphics performance in mobile form factors. - Panther Lake's CPU architecture consists of "Cougar Cove" P-cores, which offer a 5-10% IPC uplift over the preceding "Lion Cove" cores, and "Darkmont" E-cores that feature a wider pipeline and faster vector execution units than their "Skymont" predecessors. - The performance difference between Panther Lake's U-series and H-series is substantial, with the Core Ultra 7 355 (U-series) trailing the Core Ultra X7 358H (H-series) by 30-50% in multi-threaded workloads. This gap is largely attributed to the higher Turbo Boost potential in the H-series chips.
