Intel wins advanced packaging work
Reports say Intel has landed AI-chip packaging contracts with Google and Amazon, positioning it as a credible alternative to TSMC in advanced packaging—a layer increasingly decisive for accelerator and DPU availability. That suggests firms evaluating procurement should treat packaging capability as a sourcing dimension, not just raw manufacturing node performance. (vietnam.vn, semiwiki.com)
Intel is in talks to package custom artificial intelligence chips for Google and Amazon, giving buyers another option beyond Taiwan Semiconductor Manufacturing Co. (techspot.com) Advanced packaging is the step that connects multiple chip pieces, memory stacks, and wiring into one finished processor. CNBC reported on April 8 that Nvidia has already reserved most of Taiwan Semiconductor’s top packaging capacity, while Intel has packaging customers including Amazon and Cisco. (cnbc.com) The current report centers on Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, and its newer EMIB-T version, which Intel says is designed for future high-bandwidth memory needs. Intel presented EMIB-T publicly at Foundry Direct Connect on April 29, 2025, alongside new Foveros packaging options. (intc.com) Artificial intelligence chips increasingly come as “chiplets,” or several smaller dies linked inside one package, because a single giant die is harder to build and more expensive to yield. Ars Technica reported on April 7 that Intel has poured billions into packaging capacity in New Mexico, where Fab 9 and Fab 11X now support that business. (arstechnica.com) Intel’s finance chief Dave Zinsner said on March 4 that the company was close to closing packaging deals worth billions of dollars a year. He also said on Intel’s January 22 earnings call that packaging revenue should arrive before “meaningful wafer revenue,” and he raised his outlook from hundreds of millions of dollars to well above $1 billion. (theregister.com, intel.com) That sequence matters for Intel because its foundry push has struggled to land large outside manufacturing customers for leading-edge wafers. Packaging gives Intel a way to sell a narrower service first, without asking Google or Amazon to move an entire chip design onto an Intel process node. (cnbc.com, intel.com) It also matters for cloud companies because supply constraints have shifted from the transistor layer to the assembly layer. Taiwan Semiconductor’s packaging chief told CNBC that its Chip-on-Wafer-on-Substrate, or CoWoS, capacity is growing at an 80% compound annual rate, a sign of how fast demand has outrun supply. (cnbc.com) Google already widened another part of its Intel relationship on April 9, when CNBC reported that Google committed to multiple generations of Intel Xeon 6 central processing units for artificial intelligence data centers. No financial terms or timeline were disclosed. (cnbc.com) The packaging talks are still reported talks, not announced contracts, and neither Google nor Amazon has publicly confirmed them. If they turn into signed deals later in 2026, the contest over artificial intelligence chips will hinge not only on who prints the silicon, but also on who can assemble it at scale. (trendforce.com, techspot.com)