TSMC targets 70% 2nm growth
- Taiwan Semiconductor Manufacturing Co. said its 2-nanometer output should grow about 70% a year through 2028 after starting mass production in 2025. - Senior vice president Cliff Hou said five fabs will ramp 2nm in 2026, while Arizona’s first fab is set to lift output 80%. - Packaging, not wafers, is emerging as the tighter constraint for AI chips in the U.S. and Taiwan. (technode.com)
Taiwan Semiconductor Manufacturing Co. says its 2-nanometer chip capacity will grow about 70% a year from 2026 through 2028 as it races to meet artificial-intelligence demand. (technode.com) (economictimes.indiatimes.com) The company’s 2nm process entered mass production in the second half of 2025, and its N2P follow-on is scheduled for volume production in the second half of 2026. (tsmc.com 1) (tsmc.com 2) Cliff Hou, a TSMC senior vice president, said five fabs are set to enter ramp-up to mass production in 2026, which TechNode described as the company’s fastest advanced-node expansion on record. (technode.com) TSMC’s Arizona site is expanding too. The company says its Phoenix plan now includes six wafer fabs, two advanced-packaging facilities and an research-and-development team center, with total investment rising to $165 billion. (tsmc.com) That Arizona buildout is staggered by process generation: the first fab is producing 4nm chips, the second is planned for 2nm and 3nm in 2028, and a third fab is slated for the most advanced process then available in the U.S. (tsmc.com) A “nanometer” label is chip-industry shorthand for a manufacturing generation, not a literal ruler measurement. Smaller generations usually let designers pack in more transistors, which can improve speed, cut power use, or both. (tsmc.com 1) (tsmc.com 2) The next steps are already mapped out. TSMC debuted A13 on April 22, 2026, and said A14 remains planned for production in 2028, extending its roadmap beyond the first 2nm wave. (tsmc.com 1) (tsmc.com 2) The harder part is no longer only making wafers. TechNode and DigiTimes both reported that advanced packaging capacity, including CoWoS and local outsourced assembly and test support, is lagging the wafer ramp. (technode.com) (digitimes.com) That mismatch matters for AI chips because the processor die, memory and connections are often combined in one package. TSMC said at its 2024 symposium that it was pairing leading-edge silicon with advanced packaging and 3D chip-stacking to serve AI customers, and that gap is now shaping how fast supply can actually reach buyers. (tsmc.com) (digitimes.com) For now, TSMC is telling customers it can keep pushing the front edge forward. The question moving into 2027 is whether packaging lines can scale as quickly as the 2nm fabs they are supposed to feed. (technode.com) (tsmc.com)
