Researchers Unveil 1nm Transistor
A team of Chinese researchers has unveiled what is claimed to be the world's smallest ferroelectric transistor, featuring a 1-nanometer gate length. The breakthrough in transistor size could have significant implications for future silicon roadmaps. The ultra-low power consumption of the component makes it potentially suitable for edge computing and Internet of Things (IoT) devices.
The core innovation of the Peking University and Chinese Academy of Sciences design is its ultra-low 0.6-volt operating requirement. This overcomes a major power-consumption hurdle, as modern logic functions at ~0.7 volts while non-volatile memory like NAND flash can require 5 volts or more, necessitating inefficient step-up circuits. This breakthrough moves beyond traditional silicon, which suffers from quantum tunneling and current leakage at such small scales. The researchers, led by Qiu Chenguang and Peng Lianmao, instead utilized a molybdenum disulfide (MoS2) channel and a metallic single-walled carbon nanotube as the gate electrode to achieve stable performance. Ferroelectric transistors (FeFETs) are notable for their ability to act as both a processing unit and non-volatile memory, retaining data without power. This dual-purpose function enables "in-memory computing," an architecture that mimics the human brain's integrated memory and processing, which is considered a promising path for future AI hardware. The resulting device demonstrates superior memory performance, including a rapid programming speed of 1.6 nanoseconds and a current on/off ratio of two million to one. The researchers state the underlying principles are compatible with current industrial manufacturing processes. Eliminating the voltage mismatch between logic and memory addresses a critical efficiency bottleneck. In today's AI chips, an estimated 60-90% of total power is consumed by data transfer between separate processor and memory units, rather than on computation itself. This development arrives as the semiconductor industry confronts the physical limits of silicon, which has caused the pace of Moore's Law to slow. While a 1nm gate was previously created by a Berkeley Lab team in 2016, this latest work's focus on solving the power and voltage gap represents a significant step toward practical application in next-generation chips.
