TSMC’s 2029 roadmap

TSMC used its April 22, 2026 North America Technology Symposium to map out chipmaking nodes through 2029 — and left High Numerical Aperture extreme ultraviolet lithography off the near-term plan. (tsmc.com) A chip “node” is the manufacturing recipe for packing more transistors into the same area, which usually raises speed or cuts power use. TSMC said its new A13 node is a direct shrink of A14, with 6% area reduction, up to 15% speed gain at the same power, or up to 30% lower power at the same speed. (tsmc.com) TSMC’s public roadmap now stretches from N2 and N2P to N2X, A16, A14, A13, N2U and A12, with A16 moved to 2027 after the company had introduced it in April 2024 as a 2026 production technology. TSMC’s R&D page also says work is already underway on nodes beyond A14. (tsmc.com 1) (tsmc.com 2) The lithography fight underneath that roadmap is about the lens opening on the machines that print chip patterns with extreme ultraviolet light. ASML says its High-NA tools use 0.55 numerical aperture optics and can print features 1.7 times smaller in a single exposure than its older NXE systems. (asml.com 1) (asml.com 2) TSMC’s choice means it is still betting that today’s Low-NA extreme ultraviolet systems, plus process tweaks and packaging, can carry its leading-edge roadmap for several more years. Tom’s Hardware reported the company is sticking with Low-NA EUV for A14, A13 and A12 rather than adopting High-NA in the near term. (tomshardware.com) That matters because ASML has positioned High-NA for high-volume manufacturing in 2025 and 2026, starting at the 2 nanometer logic generation. If the biggest foundry delays that transition, demand for the newest scanners can shift toward rivals and research lines before it reaches mainstream volume. (asml.com 1) (asml.com 2) Intel has been the most visible early High-NA adopter. ASML said it shipped the first modules of its first High-NA system to Intel in December 2023, and later opened a joint High-NA lab with imec in 2024 to let chipmakers and tool suppliers test the platform. (asml.com) (asml.com) TSMC is not standing still on scaling while it waits. Its A16 announcement in 2024 paired nanosheet transistors with backside power delivery, and its A14 announcement in 2025 targeted production in 2028 with up to 15% speed improvement, up to 30% lower power, and more than 20% higher logic density than N2. (tsmc.com) (tsmc.com) The roadmap also shows TSMC leaning on more than transistor shrinks alone. The company’s symposium materials and product pages frame advanced packaging and 3D integration as part of the same pitch to artificial intelligence and high-performance computing customers. (tsmc.com) (tsmc.com) For customers designing chips now, the signal is simple: TSMC’s next several generations are being planned around tools already proven in volume fabs, not around a rapid switch to High-NA. That keeps the 2029 roadmap centered on manufacturing cost, yield and integration choices as much as on raw lithography resolution. (tomshardware.com) (overclock3d.net)