Siemens Uses AI for Chip Design
Siemens announced it is accelerating integrated circuit design by incorporating agentic AI into its Questa One platform. The company stated the AI-driven workflows are designed to speed up the verification process and achieve faster, more trusted register-transfer level (RTL) sign-off.
The newly announced "Questa One Agentic Toolkit" is designed to combat the widening "verification productivity gap," a major bottleneck in semiconductor development where the complexity of verifying chip designs outpaces the growth of engineering resources. This challenge is intensifying with the rise of 3D ICs and chiplet-based architectures. Agentic AI introduces autonomous software agents that can reason, plan, and execute complex multi-step verification tasks with configurable human oversight. This marks a shift from simple automation to goal-driven agents that can decompose tasks, adapt strategies, and learn from previous runs to find bugs faster. The toolkit is part of Siemens' broader "Fuse EDA AI" system, which creates a centralized data lake from a company's own design data to continuously train the AI models. This allows the AI to automate the generation of verification components like RTL code, testbenches, and assertions based on natural language specifications. This move places Siemens in direct competition with other major Electronic Design Automation (EDA) players like Synopsys and Cadence, who are also heavily investing in agentic AI to transform chip design. The entire industry is moving toward this new paradigm to handle designs that now contain billions of transistors. The AI-powered workflows can be deployed securely either on-premises or in the cloud, ensuring that a company's proprietary chip design data remains protected. Early access to the Siemens EDA AI system is currently available, with the full Questa One solution expected in June 2025.
