TSMC capacity tightens
Analysts say TSMC’s leading-edge capacity is largely sold out through 2027 as AI demand soaks wafer and packaging slots, making advanced silicon a constrained resource for infrastructure projects. The finding is framed as a structural bottleneck for specialised compute that can push procurement lead times and prices higher across FPGA, SmartNIC and accelerator programs. (seekingalpha.com)
Taiwan Semiconductor Manufacturing’s most advanced chipmaking and packaging lines are tightening as artificial intelligence customers lock in supply through 2027. (cnbc.com) Taiwan Semiconductor Manufacturing, or TSMC, is the world’s biggest contract chipmaker, and its advanced packaging business binds multiple chips together so they can act like one larger processor. TSMC says Chip on Wafer on Substrate, or CoWoS, is one of the 3DFabric technologies it uses for high-performance products. (tsmc.com) That packaging step has become a choke point as Nvidia and other data-center chip buyers order more artificial intelligence processors. CNBC reported on April 8 that Nvidia had reserved a majority of TSMC’s most advanced packaging capacity, citing TSMC North America packaging executive Paul Rousseau. (cnbc.com) Rousseau told CNBC that CoWoS capacity is growing at an 80% compound annual growth rate, and TSMC’s investor site shows the company is due to give updated guidance on April 16, 2026. TSMC’s last posted quarterly guidance pointed to first-quarter 2026 revenue of $34.6 billion to $35.8 billion. (cnbc.com) (tsmc.com 1) (tsmc.com 2) The bottleneck is not only about wafers cut from silicon; it is also about the final assembly that lets giant artificial intelligence chips talk to stacks of high-bandwidth memory. TSMC’s annual report says demand for its leading-edge logic and advanced packaging helped lift 2024 revenue by 30% in U.S. dollar terms. (tsmc.com) That squeeze reaches beyond the largest graphics processor programs. Analysts and supply-chain trackers have said advanced packaging shortages can spill into field-programmable gate arrays, Smart Network Interface Cards, and custom accelerators because those products compete for similar substrate, interposer, and assembly capacity. (trendforce.com) (tsmc.com) TSMC is still expanding. Its 2024 annual report says volume production of its 2-nanometer process is on track for the second half of 2025, and A16, a separate process aimed at high-performance computing, is scheduled for volume production in the second half of 2026. (tsmc.com) The company’s business mix shows why those lines are under pressure. TSMC said 3-nanometer technology represented 18% of total wafer revenue in 2024, and high-performance computing was one of the drivers of that demand. (tsmc.com) Rivals are trying to turn the shortage into an opening. Intel says its foundry packaging lineup includes Embedded Multi-die Interconnect Bridge, or EMIB, and Foveros Direct, two methods for linking chiplets inside one package, while CNBC reported Intel is pitching those capabilities to customers that want an alternative to TSMC. (intel.com) (cnbc.com) For cloud builders and hardware startups, the practical effect is slower procurement and less flexibility on launch schedules. Until TSMC’s new packaging lines and outside partners add enough output, the limiting factor for advanced compute will remain not just chip design, but who can secure a slot on the factory calendar. (cnbc.com) (trendforce.com)
