TSMC Sales Beat, Intel Eyes Packaging
Taiwan Semiconductor (TSMC) posted a 35% year‑over‑year revenue jump in Q1 as AI demand kept orders robust despite capacity constraints. Intel says advanced packaging—its EMIB‑T approach—could be a meaningful revenue stream as customers look for alternatives to constrained CoWoS capacity at TSMC (reuters.com) (startupnews.fyi).
The bottleneck in artificial intelligence chips is no longer just making the silicon. It is also stitching giant chips and stacks of memory together after the wafers come out of the factory, and that step is suddenly valuable enough that Intel thinks it can sell it as a business of its own. (intel.com) Taiwan Semiconductor Manufacturing, the company that builds chips for Nvidia and Apple, said on April 10 that its January-through-March 2026 revenue reached NT$1.134 trillion, up 35.1% from a year earlier. March alone was NT$415.19 billion, up 45.2% from March 2025. (tsmc.com) Reuters reported that Wall Street had expected about NT$1.12 trillion for the quarter, so Taiwan Semiconductor Manufacturing came in ahead of forecast. The company gave only monthly revenue, not full quarterly profit, but the sales number was enough to show demand for artificial intelligence chips stayed hot into early 2026. (reuters.com) The reason packaging matters is that the fastest artificial intelligence chips are no longer one big slab of silicon. They are more like a city block built from smaller buildings, with logic chips, memory stacks, and links between them all packed into one module. (intel.com) Taiwan Semiconductor Manufacturing’s best-known answer is called Chip-on-Wafer-on-Substrate, which is the method Nvidia uses for many graphics processing units tied to high-bandwidth memory. That packaging has been in short supply for more than a year because artificial intelligence accelerators need huge amounts of memory bandwidth and power in a very tight footprint. (reuters.com) Intel is pushing a rival method called Embedded Multi-die Interconnect Bridge-T. In plain English, it uses small silicon bridges inside the package instead of a full interposer, and Intel says the “T” version adds through-silicon vias so power can move more directly into memory-heavy designs. (intel.com) Intel says Embedded Multi-die Interconnect Bridge-T can already build packages larger than six times a reticle, which is the maximum image size a chipmaking tool can print in one shot, and that it should scale past eight times a reticle in 2026. That pitch is aimed directly at artificial intelligence customers trying to build ever-larger processors without waiting for more Taiwan Semiconductor Manufacturing capacity. (intel.com) That is why these two updates fit together. Taiwan Semiconductor Manufacturing’s revenue jump shows the artificial intelligence order book is still full, and Intel’s packaging push shows the shortage has moved downstream from wafer fabrication to the final assembly step that turns separate chips into one usable engine. (tsmc.com) (intel.com) If Intel can win packaging work even when it does not make the main chip, it gets a new revenue stream without first overtaking Taiwan Semiconductor Manufacturing in leading-edge manufacturing. If Taiwan Semiconductor Manufacturing expands Chip-on-Wafer-on-Substrate fast enough, it keeps more of the artificial intelligence stack inside its own orbit. (intel.com) (reuters.com) For buyers like Nvidia, Advanced Micro Devices, and custom chip teams at cloud companies, the practical question is simpler than the acronyms. Who can deliver the most compute and memory in the same package, in the biggest volume, without making them wait another two or three quarters. (reuters.com) (intel.com)
