Chip‑package bottleneck
Reports say NVIDIA is reserving the majority of CoWoS (chip‑on‑wafer‑on‑substrate) capacity, which is worsening AI hardware shortages and could lead to construction backlogs and higher costs for server builders. The capacity hold has been flagged as a persistent supply constraint as demand for AI accelerators rises. (x.com)
Nvidia has locked up most of Taiwan Semiconductor Manufacturing Co.’s top chip-packaging capacity, tightening a supply choke point for artificial intelligence hardware. (cnbc.com) Chip packaging is the step that connects finished silicon and high-bandwidth memory into a working processor module. TSMC’s North America packaging head, Paul Rousseau, told CNBC its Chip on Wafer on Substrate, or CoWoS, business is growing at an 80% compound annual rate. (cnbc.com) Rousseau said Nvidia has reserved a majority of TSMC’s most advanced packaging capacity. DigiTimes reported on April 10 that the shortage is severe enough to leave global advanced-packaging supply in “severe shortage” as artificial intelligence demand rises. (cnbc.com) (digitimes.com) That bottleneck sits after the wafer fab and before a server builder can ship a machine. If packaging slots are full, cloud companies and server makers can have finished chips waiting for assembly, testing, and delivery. (cnbc.com) The squeeze has been building alongside Nvidia’s Blackwell rollout. Nvidia said in its fiscal 2025 annual report that it began shipping production systems based on Blackwell in the fourth quarter of fiscal 2025, adding a new wave of demand for advanced packaging and memory-heavy designs. (sec.gov) Nvidia’s own numbers show how much compute demand has surged. The company’s data-center revenue reached $115.2 billion in fiscal 2025, up 142% from a year earlier, while fourth-quarter data-center revenue rose 93% year over year to $35.6 billion. (sec.gov) Taiwan Semiconductor Manufacturing is expanding to catch up, but not quickly enough to erase the near-term constraint. CNBC reported that TSMC is ramping two new packaging sites in Taiwan and is starting its first U.S. advanced-packaging facilities in Arizona this year. (cnbc.com) The United States still does not have a full domestic path for these chips today. CNBC reported that even chips made at TSMC’s Arizona fab still largely need to go back to Asia for advanced packaging, while TrendForce reported in December that large-scale CoPoS output in Arizona is expected around the end of 2028. (cnbc.com) (trendforce.com) Intel is the main alternative supplier cited in the latest reporting. CNBC said Intel’s packaging customers include Amazon and Cisco, and that Elon Musk tapped Intel on April 8 for packaging work tied to chips for SpaceX, xAI, and Tesla. (cnbc.com) For server builders, the result is less about transistor supply than about queue position at the packaging line. Until new capacity opens in Taiwan and Arizona, the fastest-growing part of the artificial-intelligence chip market will keep depending on a manufacturing step most buyers never see. (cnbc.com)
