Soitec monopolizes photonics SOI

Silicon photonics sounds like a chip niche. It isn’t. It is becoming one of the main ways AI systems move data without burning absurd amounts of power. The quiet part is the wafer underneath — the photonics-grade silicon-on-insulator substrate that the photonic circuit gets built on. And that is where Soitec has ended up with unusual leverage: not because of one splashy announcement, but because more of the ecosystem now seems to start from its Photonics-SOI platform. ### What is the actual claim here? The clean version is not “Soitec just won the market today.” The cleaner version is that Soitec has spent years becoming the de facto upstream supplier for high-end photonics SOI wafers, and the recent AI-optics wave is making that position much more visible. Soitec itself now describes sales in Q4 of fiscal 2025. ### What does Photonics-SOI actually do? A silicon photonics chip routes light through waveguides, modulators, detectors, and other optical structures etched into silicon. That only works well if the starting wafer is extremely controlled — especially the top silicon layer and buried oxide. Smart Cut is Soitec’s layer-transfer process for building that engineered stack with tight thickness control and uniformity at volume. Basically, if the wafer is off, the optics are off. ### Why does that create so much power? Because substrates are upstream and sticky. Foundries can change packaging partners, tweak process modules, or add design services. Swapping the base wafer platform is harder, especially once process design kits, yields, and reliability data are built around a certain substrate recipe. Soitec has also been in photonics SOI for roughly two decades and keeps stressing that it suddenly stops being a lab project and becomes a capacity problem. ### Are TSMC, Intel, GF, and Tower all in this lane? Yes — but in different ways. Tower already has silicon photonics in high-volume production on 200mm and launched a standard 300mm SiPho offering in November 2024. GF has long included silicon photonics in its SOI supply agreements with Soitec. TSMC is pushing its COUPE photonic-engine that the foundry and packaging layer is getting more serious about optical I/O. ### Why is AI the accelerant? Because electrical links are turning into a tax. As accelerators get packed tighter, moving bits between chips and racks eats power, space, and latency budget. Soitec and Yole both frame silicon photonics as a way to cut latency and energy in optical transceivers and future co-packaged optics. Soitec even pointed to up to 30% energy savings for CPO architectures in its March 19, 2025 statement around AI datacenters. ### So is this really a monopoly? “Monopoly” is stronger than the public evidence cleanly supports. There are other SOI suppliers in the world, and domestic Chinese work on 300mm SOI keeps advancing. But for leading-edge, high-uniformity photonics SOI used by top-tier foundries, Soitec looks much closer to a dominant default supplier than to one vendor among many. That is the important distinction. ### Where does the leverage show up next? Probably not in chip branding. It shows up in ecosystem bargaining power — who gets qualified first, who can promise volume, and which packaging, test, and chiplet partners align around the substrate that already has customer trust. When the bottleneck is optical interconnect scale-up, the company selling the starting wafer gets a louder voice than people usually notice. ### Bottom line? This is a supply-chain story disguised as a photonics story. The headline is not that Soitec suddenly seized silicon photonics in one week. It is that AI is exposing how much of the optical stack may already depend on one substrate specialist.