TSMC bets on packaging, 2nm growth
- Taiwan Semiconductor Manufacturing Co. said its 2-nanometer chip capacity will grow 70% annually through 2028 as five fabs enter volume production in 2026. - Senior vice president Cliff Hou said first-year 2nm output, which started in fourth-quarter 2025, should run 45% above 3nm’s 2023 debut. - TSMC is also racing to expand CoWoS and SoIC packaging for AI chips, shifting the bottleneck beyond wafer fabrication. (taipeitimes.com)
Taiwan Semiconductor Manufacturing Co. said its 2-nanometer chip capacity will grow at a 70% compound annual rate from 2026 through 2028. (taipeitimes.com) (focustaiwan.tw) Cliff Hou, TSMC’s senior vice president and deputy co-chief operating officer, gave the forecast at the company’s technology symposium in Silicon Valley last week. Five fabs are beginning 2nm volume production this year, with two in Hsinchu and three in Kaohsiung. (focustaiwan.tw) (taipeitimes.com) TSMC said 2nm production began in the fourth quarter of 2025, and first-year output is expected to be 45% higher than 3nm’s first year in 2023. The company also said 3nm capacity is still expanding at about 25% a year between 2022 and 2027. (focustaiwan.tw) (taipeitimes.com) The constraint is no longer just making the silicon. TSMC said it is ramping advanced packaging too, with chip-on-wafer-on-substrate, or CoWoS, capacity growing more than 80% annually from 2022 to 2027 and system-on-integrated-chips, or SoIC, rising more than 90% a year. (taipeitimes.com) (focustaiwan.tw) Packaging is the step that connects separate pieces of silicon and memory into one working module. TSMC says CoWoS is used for high-performance computing such as artificial intelligence and supercomputing, while SoIC is part of its 3D stacking lineup for higher compute density and lower latency. (tsmc.com 1) (tsmc.com 2) That helps explain why TSMC has been lifting spending plans beyond pure wafer capacity. On April 17, chief executive C.C. Wei raised the company’s 2026 revenue growth forecast to above 30% and pushed capital spending toward the high end of its US$38 billion to US$42 billion range, citing robust artificial-intelligence chip demand. (taipeitimes.com) Wei said this month that advanced packaging capacity for AI chips remained tight, and TSMC is building a new pilot line using chip-on-panel-on-substrate technology that should enter volume production in the next few years. He also said customers were watching rival packaging options from Intel. (taipeitimes.com) The boom is spilling into Taiwan’s broader economy. CRIF Taiwan forecast this week that exports will reach NT$27.5 trillion, or about US$860.6 billion, in 2026, after first-quarter exports rose 51.1% year over year to a record NT$6.26 trillion. (taiwannews.com.tw) (news.ltn.com.tw) TSMC’s overseas fabs are growing too, but the company’s latest message was that leading-edge growth still depends on adding both wafer starts and the packaging that turns those wafers into AI accelerators. Arizona’s first fab is expected to lift output 80% this year, and Kumamoto’s first fab is projected to raise output 130% from 2025. (focustaiwan.tw) (taipeitimes.com) The result is a chip race that now runs through the back end as much as the front end. TSMC is not just betting that customers want more 2nm wafers in 2026; it is betting they will pay for the packaging needed to make those wafers useful. (taipeitimes.com) (tsmc.com)