ESP32‑S31: RISC‑V MCU upgrade

Espressif’s official ESP‑IDF repository now contains a dedicated esp32s31 soc include directory with HAL/driver entries named for JPEG, EMAC, IEEE802.15.4 and other peripherals, indicating upstream SDK support is already being added to the master branch. (github.com) The esp-idf soc_caps header for the S31 and community extracts show RISC‑V–specific macros present in the tree: support for a CLIC interrupt controller, a dedicated low‑power core, hardware FPU and position‑independent executable support (RV32IMAFCP) are defined in the S31 files. (github.com) Header and forum traces attribute a SOC_GPIO_PIN_COUNT of 63 to the S31 with a maximum usable IO range reported as 62 pins, which would be the largest GPIO count Espressif has exposed in its ESP32 lineup to date. (esp32.com) The presence of esp_hal_jpeg in the S31 folder plus Espressif’s esp_new_jpeg developer blog shows the company is integrating a dedicated JPEG HAL and optimized JPEG software into the SDK stack for chips that provide JPEG acceleration. ( ) Reporting and code comments link the S31’s design lineage to the ESP32‑P4 family and community posts note P4‑class features (media accelerators and a high‑performance/low‑power core split), while P4 documentation and vendor boards list the P4’s dual RISC‑V core clocking up to ~400 MHz. ( ) As of the CNXSoft report (March 24, 2026) the S31 appears in SDK sources and community bring‑up threads but lacks a dedicated product page or published datasheet on Espressif’s public product listings, leaving commercial availability and pricing unannounced. ( )