Intel advances PowerVia 18A and DSA‑enabled 14A to raise transistor density

A modern logic chip is a traffic problem: transistors do the computing, but metal wires have to bring them power and carry signals. Intel is betting that moving some power wiring to the back of the chip will free up room on the front for denser logic. (intel.com 1) (intel.com 2) That backside-power approach is called PowerVia on Intel 18A. Intel says it improves standard-cell utilization by 5% to 10% and delivers up to a 4% performance gain at the same power by cutting voltage drop and routing congestion. (intel.com 1) (intel.com 2) Intel pairs PowerVia with RibbonFET, its gate-all-around transistor design. Instead of a fin-shaped channel, the gate wraps around stacked ribbons, which gives tighter control of current as features shrink. (intel.com 1) (intel.com 2) The company says those two changes together make Intel 18A its biggest transistor shift since FinFET in 2011. Intel’s platform brief says 18A offers up to 15% better performance per watt and up to 30% better chip density than Intel 3. (intel.com) (intel.com) Intel is already extending that platform with 18A-P and 18A-PT, while previewing 14A and 14A-E as the next step. On its foundry roadmap page, Intel says 18A is ready for full product design starts and that customers can begin engagement on 14A now. (intel.com) (intel.com) On 14A, Intel plans to move from PowerVia to PowerDirect, which it describes as a second-generation backside-power network. Intel also says 14A will use RibbonFET 2 and a new “Turbo Cells” option to tune blocks for either speed or efficiency. (intel.com) (forbes.com) At Intel Foundry Direct Connect 2025 on April 29, 2025, the company said 14A is designed for 15% to 20% better performance per watt than 18A, 25% to 35% lower power, and 1.3x higher transistor density. Industry coverage from that event also said Intel had produced early 14A wafers and was working with lead customers. (forbes.com) (electronics360.globalspec.com) (trendforce.com) The manufacturing tradeoff is cost. Intel’s own materials say 14A is where it transitions to high-numerical-aperture extreme ultraviolet lithography, a newer generation of chip-printing tools that can draw finer features but come with much higher equipment costs. (intel.com) (forbes.com) That makes the density argument central to Intel’s sales pitch. If backside power frees routing space and reduces the number of patterning steps needed elsewhere, Intel can argue that a more complex transistor stack still produces competitive cost per function. (intel.com) (ieeexplore.ieee.org) Intel is also selling geography along with process technology. Its 18A page calls the node the earliest available sub-2-nanometer advanced node manufactured in North America, a point aimed at customers that want a U.S.-based alternative to Asian foundries. (intel.com) The thread running through 18A and 14A is simple: move power out of the way, fit in more useful circuitry, and make the economics work well enough to win outside customers. Intel’s roadmap says the design work is open now; the harder part is proving those density claims at production scale. (intel.com) (intel.com)