TSMC posts 35% revenue surge — packaging bottleneck
TSMC reported a 35% year-on-year revenue rise in Q1, driven by strong AI‑chip demand, but advanced packaging—especially CoWoS capacity—remains a critical bottleneck as customers reserve limited slots. Competitors are pursuing alternatives, with Intel’s EMIB‑T packaging set for fab rollout and reports of expanded Arizona investments as the industry tries to replicate TSMC’s surrounding ecosystem. (qz.com) (digitimes.com) (tomshardware.com)
TSMC just showed that the hard part of the artificial intelligence chip boom is no longer only making the silicon. In the quarter that ended March 31, 2026, it posted NT$1.13 trillion in revenue, up 35% from a year earlier, while March alone rose 45.2%. (tsmc.com) (cnbc.com) The surprise is where the jam is forming. Companies can get wafers from Taiwan Semiconductor Manufacturing Company, but they still need advanced packaging to turn those wafers into giant artificial intelligence processors that can talk to memory and the rest of a server. (cnbc.com) Advanced packaging is the step where several small pieces are wired together into one big product, like mounting multiple engine parts into a single finished car. That matters because modern artificial intelligence chips are too large and power-hungry to stay on one simple piece of silicon. (cnbc.com) (intel.com) TSMC’s key method here is called Chip on Wafer on Substrate, which it shortens to CoWoS. The company’s North America packaging head, Paul Rousseau, said CoWoS demand is growing at an 80% compound annual rate. (cnbc.com) That speed is why customers are fighting over slots instead of only over chips. CNBC reported that Nvidia has reserved the majority of TSMC’s most advanced packaging capacity, which leaves less room for everyone else building artificial intelligence hardware. (cnbc.com) So the bottleneck has moved one station down the assembly line. TSMC is ramping two new packaging sites in Taiwan and building its first United States advanced packaging facilities in Arizona this year. (cnbc.com) That Arizona push is about more than geography. Packaging works best when the chip factory, the testing lines, the materials suppliers, and the engineers sit close together, which is the ecosystem TSMC built over decades in Taiwan and is now trying to copy in the desert. (cnbc.com) Intel sees an opening in that traffic jam. Its Embedded Multi-die Interconnect Bridge technology, called EMIB, is a different way to connect several chip pieces inside one package, and Intel says the newer EMIB-T version will scale past 8 times the reticle size this year for artificial intelligence and high-performance computing designs. (intel.com) Intel already has a high-volume advanced packaging site in Rio Rancho, New Mexico, after opening Fab 9 alongside Fab 11X as a co-located packaging complex. That gives customers a United States option while TSMC races to add Arizona capacity. (intel.com) (cnbc.com) The result is that TSMC’s 35% revenue jump is not really a story about unlimited supply. It is a story about one part of the chip business growing so fast that the scarcest product in artificial intelligence may be the final assembly slot, not the wafer itself. (tsmc.com) (cnbc.com)
