Siemens and TSMC deepen design ties

Siemens and Taiwan Semiconductor Manufacturing Co. said on April 22 they are extending their chip-design partnership to push more artificial intelligence into the software engineers use before a chip ever reaches a fab. (news.siemens.com) In semiconductor design, electronic design automation software is the toolchain that turns circuit ideas into layouts a factory can build, and design-rule checks are the tests that flag shapes or spacing a fab cannot reliably manufacture. Siemens said the new work with TSMC covers AI-assisted fixing of those rule violations and integration of its Fuse EDA AI system across the workflow. (news.siemens.com) TSMC said Siemens is one of the partners in its Open Innovation Platform ecosystem, which is how the foundry qualifies outside tools and design flows for customers using its manufacturing processes. Siemens said its tools now carry certifications tied to TSMC’s N3A, N3C, N2P, A16 and A14 technologies. (news.siemens.com) Those names matter because they are the process generations chip companies are targeting for artificial intelligence, high-performance computing and other advanced chips, where each design pass is expensive and rework can delay production. TSMC used its April 22, 2026 North America Technology Symposium to introduce A13 as the next step after A14, underscoring how quickly the roadmap is moving. (pr.tsmc.com) The immediate pitch is speed and alignment: Siemens said TSMC is using Siemens Calibre software to automate multi-step physical-verification work and Aprisa software to surface design information, recommendations and command execution during digital implementation. The goal is to cut design cycles before tapeout, the point when a chip design is sent to manufacturing. (news.siemens.com) This is also part of a broader contest around TSMC’s ecosystem. On the same day, Cadence said it had expanded its own TSMC collaboration across N3, N2, A16 and A14 with “agent-ready” digital and analog flows, and Synopsys announced new AI-powered EDA flows, IP and packaging support across TSMC’s 3-nanometer and 2-nanometer families, A16 and A14. (businesswire.com) (news.synopsys.com) Siemens and TSMC had already widened their ties in September 2025 around 3D integrated-circuit design, advanced packaging and earlier AI work, including joint validation of productivity gains in design-rule-check debugging. The April 2026 announcement extends that push from isolated certifications toward more AI-driven automation across the full design flow. (news.siemens.com 1) (news.siemens.com 2) For chip designers, the practical issue is not just whether a tool works, but whether it is already tuned and certified for the exact TSMC process they plan to buy. Siemens and TSMC are betting that tighter links between design software and manufacturing rules will keep more customers inside that combined stack as AI chips get larger, denser and harder to finish on schedule. (news.siemens.com) (businesswire.com)