AI hardware and memory moves

AI’s next cost fight is moving below the model layer, into the chips and memory modules that decide how much compute fits inside a data center power budget. (finance.yahoo.com) A chip process is the factory recipe used to print transistors, the tiny switches that do the work. On April 22, Taiwan Semiconductor Manufacturing Co. said its A13 process will enter production in 2029 and its N2U process is aimed at lower-cost chips for phones, laptops and some AI uses. (finance.yahoo.com) TSMC said it expects to keep shrinking and speeding up chips without relying on ASML’s newest High-NA extreme ultraviolet machines, which Reuters reported are more expensive than the tools TSMC already uses. TSMC’s earlier A14 node, planned for production in 2028, is advertised at up to 15% higher speed at the same power or up to 30% lower power at the same speed versus N2, with more than 20% higher logic density. (finance.yahoo.com) (tsmc.com) Memory is the short-term workspace next to the processor, and AI systems slow down when that workspace cannot feed data fast enough. On April 22, Rambus said its new SOCAMM2 chipset is built for low-power LPDDR5X memory modules in AI servers, with speeds up to 9.6 gigabits per second. (investor.rambus.com) LPDDR was built for phones, where memory sits very close to the processor and sips power. Rambus said SOCAMM2 packages that same low-power memory into a compact, serviceable server module that stays close enough to the chip to preserve signal quality at those higher speeds. (rambus.com) Rambus said the module chipset handles control, telemetry and local power delivery, which are the housekeeping jobs that keep memory stable inside a crowded server. Micron’s cloud memory chief, Praveen Vaidyanathan, said in the release that the design is aimed at “CPU-connected memory” for the next wave of AI servers. (investor.rambus.com) Cloud providers already sell AI on infrastructure economics, not just model quality. Google says its Tensor Processing Units are designed to scale cost-efficiently for training and inference, while Nvidia says inference buyers increasingly measure hardware by token cost, throughput and watts. (cloud.google.com) (developer.nvidia.com) Those metrics decide whether an AI feature can run in real time, at large scale, and at a price customers will pay. Nvidia says its latest inference systems are marketed around lower cost per token and higher tokens per watt, which is the same budget pressure TSMC and Rambus are trying to ease from different ends of the stack. (nvidia.com) TSMC is trying to lower the manufacturing bill for future processors, and Rambus is trying to lower the power and space bill for the memory feeding them. If both bets work, the next visible AI product change may look like software, but it will start in the factory and the server rack. (finance.yahoo.com) (investor.rambus.com)