Siemens, NVIDIA speed chip verification
Siemens and NVIDIA announced a verification setup that can run trillions of pre‑silicon cycles in days, a jump that addresses scale and error‑cost problems in AI chip development. The milestone highlights that industrial AI delivers fastest where complexity and expensive failures meet, and suggests factory AI use cases should target similarly high‑leverage, verifiable problems. (newelectronics.co.uk) (itwire.com)
A modern chip gets tested before it exists by running a digital stand-in, the way a flight simulator tests a plane before anyone builds the real aircraft. Siemens said on April 9 that NVIDIA is now using its Veloce proField-Programmable Gate Array Chip-Scale system to run and capture trillions of those pre-build cycles in just a few days. (siemens.com) Those test cycles are just repeated clock ticks, like frames in a movie, where engineers watch whether the design behaves correctly at each step. The reason teams care is simple: a bug found after first silicon can mean a respin that costs months of schedule and millions of dollars in masks, wafers, and lost launch time. (siemens.com) (newelectronics.co.uk) The hardware doing this is a field-programmable gate array, which is a rewireable chip engineers can reshape into a temporary version of the processor they want to build. Siemens sells that as Veloce proField-Programmable Gate Array Chip-Scale, a software prototyping platform inside its Veloce hardware-assisted verification line. (siemens.com 1) (siemens.com 2) That matters because artificial intelligence chips now look less like one giant brain and more like a crowded city of smaller blocks for memory, networking, security, and math. Siemens said the NVIDIA work used performance-optimized chip architecture to let teams run large workloads and optimize designs before first silicon arrives. (siemens.com) Siemens has been building toward this scale for a while. Its Veloce Strato Chip-Scale emulation platform, announced earlier, was built around a purpose-made CrystalX accelerator chip and can handle blade-level capacity above 40 billion gates. (siemens.com 1) (siemens.com 2) NVIDIA has been pushing the same industrial design stack from the other side. At its March 16, 2026 Graphics Technology Conference announcement, NVIDIA said Siemens was among the software companies building NVIDIA-powered tools to plan, optimize, and verify complex chip and system workflows. (nvidia.com) So this week’s announcement is not a random lab demo. It is one piece of a wider Siemens-NVIDIA partnership that both companies expanded at the January 2026 Consumer Electronics Show to cover electronic design, simulation, manufacturing, and what they called next-generation artificial intelligence factories. (nvidianews.nvidia.com) (nvidia.com) The practical win is that software teams can throw bigger real-world workloads at a chip design before tape-out, which is the point where a design gets frozen for manufacturing. Siemens said that gives NVIDIA’s teams confidence to validate software and system behavior earlier, when changing the design is still cheap. (siemens.com) (automation.com) That is why this story lands first in semiconductors and not on a factory floor with a humanoid robot. Chip verification has a clear pass-fail target, huge design complexity, and very expensive mistakes, which is exactly where industrial artificial intelligence tools tend to earn trust fastest. (newelectronics.co.uk) (nvidianews.nvidia.com)
