Edge chips choose LPDDR5X
Designers building inference chips for edge devices are favoring LPDDR5X memory instead of costly HBM to hit lower price and power targets. (x.com) That bifurcation — HBM for premium servers, LPDDR for edge — is showing up in how firms allocate silicon and packaging resources. (x.com)
AI chips that run models on robots, cameras, and factory gear are increasingly pairing their processors with LPDDR5X, a phone-style memory, instead of server-grade HBM. (micron.com) Memory is the chip’s working table: the wider it is, the more model data can move each second. LPDDR5X now reaches 10.7 gigabits per second per pin in commercial parts, while using low-power signaling built for battery devices and compact systems. (samsung.com; micron.com) HBM, or high-bandwidth memory, takes a different route. It stacks memory dies vertically and places them beside logic on a silicon interposer, a dense wiring layer, using advanced packaging such as TSMC’s Chip-on-Wafer-on-Substrate, or CoWoS. (tsmc.com; tsmc.com) That design buys enormous bandwidth for data-center chips. Nvidia says the H100 delivers 3 terabytes per second of memory bandwidth, and AMD says the MI300X ships with 192 gigabytes of HBM3 and 5.3 terabytes per second of peak bandwidth. (nvidia.com; amd.com) Edge devices usually optimize for a different constraint set: watts, dollars, thermals, and board size. Nvidia’s Jetson Thor modules, aimed at robotics and embedded systems, use LPDDR5X and offer 128 gigabytes of memory in modules configured from 40 watts to 130 watts. (nvidia.com; nvidia.com) Other inference chips show the same tradeoff, even outside tiny devices. Qualcomm’s Cloud AI 100 Ultra uses 128 gigabytes of LPDDR4x on a 150-watt card, and Hailo says its Hailo-10H edge accelerator includes a direct DDR memory interface rather than HBM-style stacked memory. (qualcomm.com; hailo.ai) The split is also showing up in packaging demand. TSMC describes CoWoS as a platform for high-performance computing that integrates logic with HBM cubes, while its roadmap calls for larger interposers and more HBM support as compute power rises. (tsmc.com; tsmc.com) That leaves memory makers and chip designers serving two markets at once. Server accelerators keep pulling scarce advanced packaging capacity toward HBM-heavy parts, while edge designs can use cheaper, lower-power LPDDR5X packages that fit robots, vehicles, and industrial boxes. (tsmc.com; samsung.com; micron.com)
